Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble (online), Sept. 6, 2021
Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.
The MOS-AK Workshop Program is available online:
https://www.mos-ak.org/grenoble_2021/
Venue: Online MOS-AK Webinar; use the online form/link below to register:
https://forms.gle/neAwxTczP9PVE7uU6
Registered MOS-AK/Grenoble participants will receive an online access link on SEPT.3 before the main event;
any related enquiries can be sent to register@mos-ak.org
-- W.Grabinski; MOS-AK (EU)
WG180821 --
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Aug 18, 2021
Aug 10, 2021
[mos-ak] Re: [Final Program] 5th Sino MOS-AK Workshop Xi'an (hybrid/online) August 11-13, 2021
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
5th Sino MOS-AK Workshop Xian
August 11-13, 2021
The Xidian University Host and local MOS-AK Organizers are providing following login information
Meeting link for 12th-13th. August
(no need to have password and can discuss/Q&A )
Meeting ID：357 1681 8021
Live channel: https://meeting.tencent.com/l/OWgMlNVDPe7E
(can not discuss just listen, password is 812813)
If anyone wants to attend MOS-AK Xian Training Course on 11th. August.
Meeting ID：716 195 769
Live channel: https://meeting.tencent.com/l/xPZezoHpYMwT
(cannot discuss, just listen, password is 210811)
Please also note that all presentation timing listed in the workshop program
is in local Chinese time zone (GMT+8)
-- Min Zhang; XMOD Technologies (CN)
-- W.Grabinski; MOS-AK (EU)
--
WG080921
On Monday, July 5, 2021 at 5:30:55 PM UTC+2 Wladek Grabinski wrote:
Arbeitskreis Modellierung von Systemen und ParameterextraktionModeling of Systems and Parameter Extraction Working Group5th Sino MOS-AK Workshop XianAugust 11-13, 2021Together with local Xidian University Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 5th Sino MOS-AK Workshop Xian workshop which will be Virtual/Online event. Scheduled, MOS-AK/Xian workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.The MOS-AK Workshop Program is available online:Venue: Hybrid event at Xidian University <xidian.edu.cn>会议场所：西安电子科技大学北校区阶梯教学楼112报告厅,西安市雁塔区太白南路2号西安电子科技大学（北校区）No.2, South Taibai Road, Xian Dianzi University, Xi'an, 710071Workshop Secretary: Meng Zhang Mobile:13619295980any related enquiries can be sent to regist...@mos-ak.orgPost-workshop publications, selected, the best papers will be selected and recommended for further publication in the renowned journal such as Weily's International Journal of Microwave and Optical Technology Letters special issue.-- Min Zhang; XMOD Technologies (CN)-- W.Grabinski; MOS-AK (EU)WG050721
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[paper] Systematic approach for IG-FinFET amplifier design using gm/Id method
Alireza Hassanzadeh and Sajad Hadidi
Systematic approach for IG-FinFET amplifier design using gm/Id method
Analog Integrated Circuits and Signal Processing (2021)
https://doi.org/10.1007/s10470-021-01917-9
EE Department, Shahid Beheshti University, Tehran, Iran
Abstract: In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using gm/Id method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based gm/Id method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from a single 1 V power supply.
Fig: gm/Id vs. normalized Id(Vbg)
[paper] Compact Model for Electrostatics of III–V GAA Transistors
Mohit D. Ganeriwala, Francisco G. Ruiz*, Enrique G. Marin* and Nihar R. Mohapatra
A unified compact model for electrostatics of III–V GAA transistors with different geometries
Journal of Computational Electronics (2021)
Published: 07 August 2021
DOI: 10.1007/s10825-021-01751-2
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, Gujarat, 382355, India
*Department of Electronics, University of Granada, Granada, Spain
Abstract: In this work, a physics-based unified compact model for III-V GAA FET electrostatics is proposed. The model considers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed first using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unified representation. The efficacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrödinger solver. The proposed model is found to be accurate for GAA FETs with different geometries, dimensions and channel materials and computationally efficient.
Fig: III–V GAA transistors with different geometries
Acknowledgements: This work is supported by the Visvesvaraya PhD scheme by MeitY, Gover nment of India Enrique G. Marin gratefully acknowledges Juan de la Cierva Incorporation IJCI-2017-32297 (MINECO/AEI).
#Tata Group Looking To Enter #Semiconductor #Manufacturing
#Tata Group Looking To Enter #Semiconductor #Manufacturing https://t.co/wRzBoxdPrf #semi https://t.co/B74v7K54NK
— Wladek Grabinski (@wladek60) Aug 9, 2021
from Twitter https://twitter.com/wladek60
August 10, 2021 at 12:19AM
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