Ranking of #top10 #foundries by revenue in 1Q21 [TrendForce]https://t.co/Vju8cxjtXl #semi #waferfab pic.twitter.com/ldAr98f7fv
— Wladek Grabinski (@wladek60) June 1, 2021
from Twitter https://twitter.com/wladek60
June 01, 2021 at 02:33PM
via IFTTT
Jun 1, 2021
Ranking of #top10 #foundries by revenue in 1Q21
from Twitter https://twitter.com/wladek60
June 01, 2021 at 02:33PM
via IFTTT
[review] CNTFET Technology for RF Applications
CNTFET Technology for RF Applications: Review and Future Perspective
Martin Hartmann1,2, Sascha Hermann1,2,3, Phil F. Marsh4, Christopher Rutherglen4,
Dawei Wang5, Li Ding6, Lian-Mao Peng6, Martin Claus7
and Michael Schröter7 (Senior Member, IEEE)
(Invited Paper)
in IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, winter 2021,
DOI: 10.1109/JMW.2020.3033781
1Center for Microtechnology, Chemnitz University of Technology, 09111 Chemnitz, Germany
2Center for Advancing Electronics Dresden, 09111 Chemnitz, Chemnitz
3Fraunhofer Institute for Electronic Nanosystems, 09126 Chemnitz, Germany
4Carbonics Inc., Culver City, CA 90230 USA
5Carbon Technology Inc., Irvine, CA 92619 USA
6Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, Department of Electronics, Peking University, Beijing 100871, China
7Chair for Electron Devices and Integrated Circuits, Technical University Dresden, 01069 Dresden, Germany
Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.
Fig: (a) sketch of a T-shape top gate on 4′′ wafer and (b) corresponding SEM image, (c) SEM image [I] in false colors depicting a multifinger buried gate CNTFET on an 8" wafer [II].
Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.
REF:
[I] C. Rutherglen et al., "Wafer-scalable aligned carbon nanotube transistors operating at frequencies of over 100 GHz", Nature Electron., vol. 2, no. 11, pp. 530-539, 2019.
[II] M. Hartmann et al., "Gate spacer investigation for improving the speed of high-frequency carbon nanotube-based field-effect transistors", ACS Appl. Mater. Interfaces, vol. 12, no. 24, pp. 27461-27466, 2020.
Virtual Si Museum /2122/ HP Calculators
My own collection of the HP Calculators. The HP 21 was my very first Hewlett-Packard calculator. Here sorted by its number with HP 15C as most recent addition:
HP 21 Second Generation HP-35
May 31, 2021
#TSMC founder doubts #US competence in #chip-making
[https://t.co/4cRTlKFKn6] #TSMC founder doubts #US competence in #chip-making https://t.co/HWpPWUnjmy #semi pic.twitter.com/GttqosRZW6
— Wladek Grabinski (@wladek60) May 31, 2021
from Twitter https://twitter.com/wladek60
May 31, 2021 at 10:40AM
via IFTTT
May 26, 2021
[Review] Nanosheet Transistors Technology
Firas N. A. Hassan Agha1, Yasir H. Naif2, Mohammed N. Shakib3
Review of Nanosheet Transistors Technology
Tikrit Journal of Engineering Sciences (2021) 28 (1): 40-48
ISSN: 1813-162X (Print) ; 2312-7589 (Online)
DOI: http://doi.org/10.25 30/tjes.28.1.05
available online at: http://www.tj-es.com
1Electrical Department/ Engineering College; Mosul University; Mosul, Iraq
2Department of Computer Engineering; Faculty of Engineering, Tishk; International University; Erbil, Iraq
3Faculty of Electrical and Electronics; Engineering Technology, University; Malaysia Pahang; Pekan, Malaysia
Abstract: Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).
Fig: Development of Field Effect Transistor from FinFET to MBCFET [Credit: Samsung]
Acknowledgment: The authors would like to thank University of Mosul for their support.
Subscribe to:
Posts (Atom)