[C4P] EuroSOI-ULIS 2021, September 1-3, 2021, Caen (F)

The Seventh Joint International EuroSOI and ULIS Conference 

will be held in hybrid format in Caen, Normandy, France

from September 1 to September 3, 2021

After a virtual 2020 edition, if sanitary condition will permit, the 2021 EUROSOI-ULIS event will be held in hybrid format. The conference will be preceded on August 31, 2021 by "The Future of Nanoelectronics Devices and Systems Beyond Moore" Workshop.

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference.
Original 2-page abstracts with illustrations will be accepted for review in pdf format.

Abstract submission is now open. The abstract submission deadline is Mai 17, 2021 Mai 31, 2021. 

More information are provided on the Conference website: 
https://eurosoiulis2021.sciencesconf.org

Papers in the following areas are solicited:

• Advanced SOI materials and structures; physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality; thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, reliability, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, Nanowire, FinFET, MuGFET, vertical MOSFET, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling; three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  

Confirmed Plenary Talks Speakers:

• Alexander Zaslavsky (Brown University, USA)
• Anne Vandooren (imec, Belgium)
• Frédéric Allibert (SOITEC, France)
• Jean-Michel Sallèse (EPFL, Switzerland)
• Sorin Cristoloveanu (IMEP Minatec, Grenoble, France)
• Sorin Voinigescu (University of Toronto, Canada)

The authors of the accepted contributions will be requested to provide a 4-page extended abstract which will be included in the Conference Technical Digest which will be published by IEEE and will be available online through IEEE Xplore. Outstanding papers will be invited for publication in a special issue of Solid-State Electronics.

The best paper award, renamed "The Androula Nassiopoulou Best Paper Award" in tribute to her, will be attributed by the SINANO Institute. The best poster award will be attributed by ELSEVIER.

We look forward to seeing you in Caen in 2021 ( https://en.normandie-tourisme.fr/unmissable-sites/caen/things-to-do/).

With best regards,
The EuroSOI-ULIS 2021 Organizing Committee

Note:
We are glad to inform you that 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Proceedings has been posted to the IEEE Xplore digital library
https://ieeexplore.ieee.org/xpl/conhome/9365069/proceeding
If you missed the last edition of EuroSOI-ULIS, do not miss the scientific articles published in the IEEE Xplore database! Many thanks to all authors and attendees for their essential contributions that endorsed EuroSOI ULIS'2020 as a successful virtual conference! Information on EuroSOI-ULIS'2020 virtual edition may be found in the IEEE EDS Newletter published in January 2021 (https://eds.ieee.org/publications/eds-newsletter ; pages  58-60)

[Workshop] Democratizing IC Design, April 7th, 2021

Solid-State Circuits Directions Workshop: Democratizing IC Design

Wednesday, April 7th, 2021 at 7:00 AM PT / 10:00 AM ET This event is free and open to all

CLICK HERE TO REGISTER

EVENT DESCRIPTION Solid-State Circuits Directions (SSCD) is a new technical committee within the IEEE Solid-State Circuits Society (related article). Its charter is to promote forward-looking topics, build new communities and stimulate interaction with others. Following SSCD’s inaugural event on hardware security, the upcoming workshop will look at the new movement toward an open-source ecosystem for integrated circuit design. Over the past several decades, society has strongly benefited from free and open-source software. More recently, the open-source spirit has expanded to hardware and has energized a new maker community that tinkers with embedded systems at the printed circuit board level. Groundbreaking developments have now also opened the door toward democratizing integrated circuit design. Last year, Google, SkyWater and efabless have partnered to launch a shuttle program based on SkyWater’s SKY130 open-source process (130 nm CMOS). This technology is offered to the open community along with a complete design flow to enable designers to implement their ideas. This workshop will provide an overview of this program and highlight upcoming opportunities to benefit from it. Finally, it will showcase specific design work delivered by the community members and articulate a call to action for volunteers to design, teach and mentor. AGENDA 7:00 AM PT- Welcome & Introductions (Boris Murmann, Stanford University) 7:05 AM PT- Fully open source manufacturable PDK for a 130nm process (Tim Ansell, Google) 7:35 AM PT- 45 Chips in 30 Days: Open Source ASIC at its best! (Mohamed Kassem, efabless) 7:55 AM PT- Design 1: Open Source eFPGA implementation in SKY130 (Xifan Tang, University of Utah) 8:25 AM PT- Design 2: Amateur Radio Satellite Transceiver (Thomas Parry, SystematIC Design) 8:55 AM PT- Call to Action: Need volunteers to design, teach and mentor 9:00 AM PT- Adjourn

[C4P] ISPS 2021 Prague, August 25–27, 2021

 15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS

ISPS 2021

Prague, 25 August – 27 August 2021

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Organised by	IET Czech Network in co-operation with the IEEE Czechoslovakia Section
Co-sponsored by	Faculty of Electrical Engineering, Department of Electrotechnology, Czech Technical University in Prague
Technical sponsor	ECPE European Center for Power Electronics e.V.
Conference website	http://technology.fel.cvut.cz/ISPS2021

BACKGROUND

The 15th International Seminar on Power Semiconductors (ISPS 2021) provides a forum for technical discussion in the area of power semiconductor devices and their applications. It is a small conference with the special flair of an atmosphere of searching deeper insight and intensive discussion.

AREAS OF INTEREST

• Power semiconductor devices (materials, physics, modelling, technology, diagnostics)
• Packaging, advanced device applications, reliability

Papers oriented in the field of power semiconductors are supposed to be presented in sessions on

• Device Physics and Technology
• Power Bipolar Devices
• Voltage-Controlled Power Devices
• Wide Bandgap Power Devices
• Power Integration
• Advanced Applications
• Packaging, Reliability & Modelling.

A round table discussion oriented on topical problems of research and education in the field of power semiconductors will be organised in the framework of the seminar.

PAPER SUBMISSION

A summary of 300–500 words (maximum two pages including figures and tables) is required for review. It should be uploaded in electronic format (.doc or .pdf files) to the ISPS 2021 easychair conference system:

http://easychair.org/conferences/?conf=isps2021

before April 30, 2021.

PUBLICATION

Presented papers will be published in the seminar proceedings, which will be distributed at the seminar registration. We are delighted to announce that the best papers presented at the conference will be invited for consideration in a special issue of the IET Power Electronics Journal dedicated to the ISPS 2021 seminar.

ORGANISING COMMITTEE

Chairman:	Prof Vítězslav Benda, FIET
Members:	Dr Vítězslav Jeřábek, MIET
	Dr Martin Molhanec
	Dr Ladislava Černá, MIET
	Dr Pavel Hrzina

Nine out of ten #chips used by #US industries are made outside the country

[https://t.co/iJTj8FNNaJ] Nine out of ten #chips used by #US industries, including automotive and defense, are made outside the country https://t.co/91uq9m2VLA#semi pic.twitter.com/jhWxs4YDy5

— Wladek Grabinski (@wladek60) March 16, 2021

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from Twitter https://twitter.com/wladek60

March 16, 2021 at 11:12AM
via IFTTT

[paper] 3D integrated GaN/RF-SOI SPST switch

Frédéric Drillet, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar and Gregory U'Ren 

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch 

International Journal of Microwave and Wireless Technologies, pp. 1–6, 2021.

*X-FAB France, Corbeil-Essonnes (F)

Abstract: This paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Fig: X-FAB 3D integration proposal cross-section (left) and the picture of a GaN coupon (right).

Acknowledgement: We would like to acknowledge the Nano2022 program for partially funding this work.

Supplementary material: The supplementary material for this article can be found at DOI: 0.101/1759078721000076