Free Webinar on @SPICE Simulation - Semiwiki https://t.co/r857oMaZjE #semi https://t.co/A867NuzVX3

Free Webinar on @SPICE Simulation - Semiwiki https://t.co/r857oMaZjE #semi pic.twitter.com/A867NuzVX3

— Wladek Grabinski (@wladek60) October 5, 2020

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October 05, 2020 at 09:49AM
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Spin-On Memory: Cerfe Labs spins out from Arm https://t.co/M9uk3GBKtG #semi https://t.co/jPr109ZlXt

Spin-On Memory: Cerfe Labs spins out from Arm https://t.co/M9uk3GBKtG #semi pic.twitter.com/jPr109ZlXt

— Wladek Grabinski (@wladek60) October 5, 2020

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October 05, 2020 at 09:33AM
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#Renesas signs deal with #opensource #ARM competitor https://t.co/RqUc0Kal7G #semi https://t.co/qHRJ7dzvD9

#Renesas signs deal with #opensource #ARM competitor https://t.co/RqUc0Kal7G#semi pic.twitter.com/qHRJ7dzvD9

— Wladek Grabinski (@wladek60) October 2, 2020

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October 02, 2020 at 04:49PM
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Łukasiewicz-Instytut Mikroelektroniki i Fotoniki - will develop Polish electronics. The pillars of the new institute will be, as before: employees, equipment and technologies. #semi https://t.co/VYeKhDf8TC

Łukasiewicz-Instytut Mikroelektroniki i Fotoniki - will develop Polish electronics. The pillars of the new institute will be, as before: employees, equipment and technologies.#semi https://t.co/VYeKhDf8TC

— Wladek Grabinski (@wladek60) October 1, 2020

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from Twitter https://twitter.com/wladek60

October 01, 2020 at 03:39PM
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[thesis] RF UTBB FDSOI MOSFET

Vanbrabant, Martin

RF characterization of the back-gate contact on Fully Depleted SOI MOSFETs

http:// hdl.handle.net/2078.1/thesis:26763

Ecole polytechnique de Louvain, Université catholique de Louvain, 2020. 

Academic year 2019–2020: Master in Electrical Engineering

Prom.: Prof. Jean-Pierre Raskin

Readers: Denis Flandre, Valeriya Kilchytska, Lucas Nyssens, Martin Rack

Abstract: Thanks to the thin buried-oxide, the UTBB FDSOI technology with a highly doped region under the BOX is one of the main candidates for future RF applications. One of the most interesting feature of this technology is the possibility to tune the threshold voltage, compensate variability issues and improve the overall device performance. In this work, the impact of the back-gate bias is mainly studied on the threshold voltage and RF FoMs of the front and back-gates.

Figure: Reconstructed (dashed) vs initial (full) Re{Yij} insaturationat VDS=0.8V, VGS=0.8V and VB=0V for a 4-port device.