Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15#semi pic.twitter.com/W5DgoT4Kul
— Wladek Grabinski (@wladek60) July 30, 2020
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July 30, 2020 at 11:22AM
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Jul 30, 2020
Chipmaker #SMIC Eyes China’s Biggest Share Sale in a Decade https://t.co/x7fWlihi15 #semi https://t.co/W5DgoT4Kul
from Twitter https://twitter.com/wladek60
July 30, 2020 at 11:22AM
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[paper] Compact Modeling of IGBT
Y. Miyaoku, A. Tone, K. Matsuura, M. Miura-Mattausch, H. J. Mattausch, and *D. Ikoma
Compact Modeling of IGBT Charging/Discharging
for Accurate Switching Prediction
IEEE J-EDS, DOI:10.1109/jeds.2020.3008919
Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan
*Denso Corp., Aichi, Japan
Abstract: The trench-type IGBT is one of the major devices developed for very high-voltage applications, and has been widely used for the motor control of EVs as well as for power-supply systems. In the reported investigation, the accurate prediction of the power dissipation of IGBT circuits has been analyzed. The main focus is given on the carrier dynamics within the IGBTs during the switching-off phase. It is demonstrated that discharging and charging at the IGBT’s gate-bottom-overlap region, where electron discharging is followed by hole charging, has an important influence on the switching performance. In particular, the comparison of long-base and short-base IGBTs reveals, that a quicker formation of the neutral region within the resistive base region, as occurring in the long-base IGBT, leads to lower gatebottom-overlap capacitance, thus realizing faster electron discharging and hole charging of this overlap region.
Fig: Studied IGBT structure with indicated current flows
Jul 29, 2020
[paper] Vertical III-V Nanowire MOSFETs on Si
Olli-Pekka Kilpi, Markus Hellenbrand, Johannes Svensson, Axel R. Persson, Reine Wallenberg, Erik Lind, Member, IEEE, and Lars-Erik Wernersson
High-Performance Vertical III-V Nanowire MOSFETs on Si With gm > 3 mS/μm
in IEEE EDL vol. 41, no. 8, pp. 1161-1164, Aug. 2020
DOI: 10.1109/LED.2020.3004716
Abstract: Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 μm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 μm, demonstrating that most of the MOSFET access resistance is located in the contact regions.
FIG: (a) of the MOSFET structure demonstrating benefit of the TiN gate metal;
(b )output characteristics of the vertical nanowire MOSFET
with 90 nanowires, LG = 25 nm and diameter 17 nm.
Acknowledgment: This work was supported in part by the Swedish Research Council, in part by the Knut and Alice Wallenberg Foundation, in part by the Swedish Foundation for Strategic Research, and in part by the European Union H2020 Program INSIGHT under Grant 688784.
“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi https://t.co/rTU6actXHx
“Entrope” High-Frequency #HF #Noise Probe – Device Lab Inc. https://t.co/GSalqQAnX1 #semi pic.twitter.com/rTU6actXHx
— Wladek Grabinski (@wladek60) July 29, 2020
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July 29, 2020 at 01:54PM
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#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi https://t.co/qxbrrmOV1j
#European Research and Innovation #R&I #Days https://t.co/BR7YIsy2xO #semi pic.twitter.com/qxbrrmOV1j
— Wladek Grabinski (@wladek60) July 29, 2020
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July 29, 2020 at 01:50PM
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