[mos-ak] [press note] 10th International MOS-AK Workshop in the Silicon Valley

 Arbeitskreis Modellierung von Systemen und Parameterextraktion

 Modeling of Systems and Parameter Extraction Working Group

 10th International MOS-AK Workshop in the Silicon Valley

 San Jose, CA, December 6, 2017 

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 10th consecutive, international compact/SPICE workshop in the USA. The event was hosted on Dec.6, 2017, by Cadence Design Systems in the Silicon Valley with is a perfect place to celebrate a decade of the MOS-AK activities in the USA. The technical program of the event was coordination by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop has received full industrial sponsorship by Cadence Design Systems (lead sponsor) and Keysight Technologies with technical program promotion provided by the IEEE EDS SC-SF Chapter,  IJHSES as well as NEEDS of nanoHUB.org

The MOS-AK workshop was opened by Hany Elhak, Cadence Design Systems, who has welcomed all the attendees and shared Cadence view on the compact modeling and its importance in the TCAD/EDA modeling/design ecosystem. A group of 40+ international academic researchers and modeling engineers attended 13 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D.

The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including: [1] J. Xie, Cadence: Verilog-A debug tool: AHDL Lint; [2] R. Radojcic et al. PDA: A Complete Learning-Based Semiconductor Parametric Testing and Device Modeling Ecosystem, from Probing to Simulation; [3] D. Celi, STM: Generation of HICUM/L2 and HICUM/L0 Geometry Scalable Model Libraries; [4] I. Radu, SOITEC: SOI technology platforms for 5G: opportunity of collaboration; [5] Mierzwinski et al. Keysight: An Overview of the HiSIM SOI/SOTB Compact Models; [6] A. Pashkovich and B. Tudor, SILVACO: Featured Circuit Simulation Using SMARTSPICE Compact Models and Verilog-A; [7] A. Asenov, Uni. Glasgow: Compact Model Requirements for TCAD Based DTCO; [8] D. Yakimets et al. imec: Enablement of compact models for ultra-scaled CMOS technologies; [9] G. Hills et al. Uni. Stanford: Rapid Co-optimization of Processing & Circuit Design to Overcome Carbon Nanotube Variations; [10] W. Grabinski, EDS DL, MOS-AK (EU): FOSS/H Tools for Compact Modeling; [11] D. Navarro et al. Uni Hiroshima: A Normally-on MOSFET Compact Model based on Surface Potential Description; [12] K.-W. Pieper, Infineon: Aging simulation with variation of several model parameters; [13] T. Nigam and A. Kerber, GLOBALFOUNDRIES: Reliability characterization of discrete devices and modeling circuit level ageing in advanced CMOS technologies. All the presentations are available online for download at <http://www.mos-ak.org/silicon_valley_2017/>. Selected best presentation will be recommended for further publication in the IJHSES.

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and open Verilog-A model directory with supporting FOSS TCAD/EDA tools. The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA and China throughout coming 2018 year, including:

• Spring MOS-AK Workshop, Strasbourg (F) March 15-16, 2018
  
• 3rd Sino MOS-AK Workshop, Beijing (CN) June, 2018
  
• MIXDES Special CM Session, Gdynia (PL) June 21-23, 2018
  
• 16th MOS-AK at ESSDERC/ESSCIRC, Dresden (D), Sept.3, 2018
  
• 11th International MOS-AK Workshop, Silicon Valley (US) Dec.2018
  

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information please visit: https://www.cadence.com

About Keysight Technologies

Keysight Technologies, Inc. (NYSE: KEYS) is a leading technology company that helps its engineering, enterprise and service provider customers accelerate innovation to connect and secure the world. Keysight's solutions optimize networks and bring electronic products to market faster and at a lower cost with offerings from design simulation, to prototype validation, to manufacturing test, to optimization in networks and cloud environments. Customers span the worldwide communications ecosystem, aerospace and defense, automotive, energy, semiconductor and general electronics end markets. Keysight generated revenues of $3.2B in fiscal year 2017. In April 2017, Keysight acquired Ixia, a leader in network test, visibility, and security. More information is available at www.keysight.com

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[Special Issue] TED on “Compact Modeling for Circuit Design"

Call for papers for 

a Special Issue of IEEE TED

on

Compact Modeling for Circuit Design

Submission deadline: April 30, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.

Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:

http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html

In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:

1. Benjamin Iniguez, URV, Tarragona (SP)
2. Yogesh Chauan, IIT Kanpur (IN) 
3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
4. Ananda Roy, Intel Corporation, Portland, OR (USA)
5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
8. Wladek Grabinski, GMC Consulting, Commugny (CH) 
9. Kaikai Xu, UEST of China, Chengdu (CN) 

Enhanced transconductance in a double-gate graphene field-effect transistor https://t.co/aVJlxjMHVj #paper https://t.co/DPbG4zxT1d

Enhanced transconductance in a double-gate graphene field-effect transistor https://t.co/aVJlxjMHVj #paper http://pic.twitter.com/DPbG4zxT1d

— Wladek Grabinski (@wladek60) December 21, 2017

from Twitter https://twitter.com/wladek60

December 21, 2017 at 03:28PM
via IFTTT

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS #Model https://t.co/KQZ8JlQV8r https://t.co/jVdRwct9J3

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS #Model https://t.co/KQZ8JlQV8r http://pic.twitter.com/jVdRwct9J3

— Wladek Grabinski (@wladek60) December 21, 2017

from Twitter https://twitter.com/wladek60

December 21, 2017 at 01:14PM
via IFTTT

[call for papers] EUROSOI-ULIS2018, Granada

Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon

Granada, Spain

on March 19-21, 2018

3rd Call for Papers 

Abstract Submission Deadline: January 12, 2018

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The template is available at the conference website: congresos.ugr.es/eurosoi-ulis2018. The accepted abstracts will be published in a Proceedings book with an ISBN. The authors of the accepted contributions will be requested to provide a 4-page paper to appear in the conference proceedings, which will be submitted to the IEEE Xplore® digital library. A selection of the presented manuscripts in the conference will be invited to submit an extended version, which after a peer-review process, will be published as a Special Issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Papers in the following areas are solicited:
• Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
• Emerging memory devices

Invited Speakers:
• Prof. Jesús del Alamo (MIT, USA): III-V CMOS: Quo vadis?
• Prof. Hiroshi Iwai (TIT, Japan): 3D scaling of Si-IGBT.
• Prof. Enrique Calleja (Uni Madrid, Spain): MBE growth of ordered InGaN/GaN nano/microrods: basics and applications.
• Prof. Edward Yi Chang (NCTU, Taiwan): High performance GaN HEMT technologies.
• Prof. Adrian Ionescu (EPFL, Switzerland): Millivolt technology for low power digital and sensing applications.
• Dr. Byungil Kwak (SK Hynix, Korea): DRAM Peripheral Transistor Scaling using logic technologies – Future Challenges.