C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan
Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations
IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020
DOI: 10.1109/TED.2020.2994018
Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.
Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched
between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI
FET. (c) Gate-stack of MFMIS FDSOI FET.
Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.
