Showing posts with label Correlation power analysis (CPA). Show all posts
Showing posts with label Correlation power analysis (CPA). Show all posts

Jul 15, 2020

[paper] Power Side-Channel Attacks in NCFET

Knechtel, Johann, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf,
Yogesh S. Chauhan, Jörg Henkel, Ozgur Sinanoglu, and Hussam Amrouch
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)
IEEE Micro, DOI 10.1109/MM.2020.3005883
Preprint arXiv:2007.03987 (2020)

Abstract: Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Fig: (a) NCFET structure,with ferroelectric layer integrated inside the transistor’s gate stack;
(b) Equivalent caps series, where the internal voltage exhibits a greater voltage (Vint  > VG)

Acknowledgments: This work was supported in part by the Center for Cyber Security (CCS) at New York University Abu Dhabi (NYUAD). The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYUAD. Besides, parts of this work were carried out on the HPC facility at NYUAD.