Showing posts with label 12nm. Show all posts
Showing posts with label 12nm. Show all posts

Sep 17, 2026

[paper] 12nm FinFETs from 292K to 10mK

D. Lee, J. Lee, L. Jin, R. Rangaraj, L. Shao and J. S. Walling
12nm FinFETs from 292K to 10mK:
Characterization and a Temperature-Continuous Compact Model for Qubit Control
Preprint arXiv:2609.11963 (19 Aug 2026)

1 Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA

Abstract: We report cryogenic characterization and compact modeling of GlobalFoundries (GF) 12LP regular-voltagethreshold (RVT) n- and p-FinFETs, measured from 292K to 10mK. Both devices retain sub-Kelvin gate control without carrier freeze-out, with the n-type device exhibiting an intrinsic subthreshold slope (SS) floor of 24.8 mV/dec. To bypass high on-chip series routing resistance that confounds peak-gm extraction, we adopt a fixed-current (3.26 μA/μm) methodology. These low current metrics inform a continuous 1.36K to 292K compact model using dynamic parameter injection, preserving room temperature process development kit (PDK) qualification.
Fig: Measured transfer characteristics at |VDS,ext| = 0.8V, shaded dark to light with increasing temperature. Drain current is normalized to gate width, so the dotted line marks the constant-current threshold criterion at ICC = 1μA/μm.

Acknowledgment: The 12nm finFET IC fabrication was provided by GlobalFoundries as part of their University Partnership Program.