[paper] Compact Modeling of Ferroelectric Devices

J. Lee, J. Kim, M. Kim, H. Kim, C. Ra, H. Choi, and J. Jeon,

“Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation,”

ACS Applied Electronic Materials, Feb. 2026,

doi: 10.1021/acsaelm.5c02300

* Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon 16419 (KR)

Abstract: This paper presents a unified compact model that comprehensively captures nonideal behaviors such as asymmetric hysteresis and minor loops of ferroelectric devices based on hafnium zirconium oxide (HfO2–ZrO2, HZO). The proposed model, based on the Preisach framework, integrates branch-dependent slopes, asymmetric coercive voltages, imprint-induced loop shifts, and low-voltage minor-loop responses into a unified analytical form. Implemented in Verilog-A, the proposed model reproduces measured polarization–voltage (P–V) characteristics of a ferroelectric capacitor (FeCAP) with higher accuracy than conventional symmetric models. Furthermore, using an identical parameter set, it consistently scales from a single device to logic, memory, and neuromorphic circuits, enabling prediction of operating characteristics and read/write margins. Owing to these capabilities, the model serves as a reliable predictive tool for circuit-level design and provides a practical pathway for process–design feedback and co-optimization.