C4P Special Issue JEDS on Compact Modeling

Call for papers for a Special Issue
of IEEE Journal of the Electron Devices Society
on “Compact Modeling of Semiconductor Devices”
Submission deadline: April 1, 2020 MAY 15, 2020

In order to exploit the full potential of semiconductor devices in circuit design, compact device models are critically needed. Compact device models are the vehicle that allow the design of circuits using the targeted devices. Predictive and physically-based compact device models are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate compact device models. 

Compact models should accurately capture the physics of the device in all operation regimes, but at the same time they should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. Furthermore, compact models can also be used as a tool to make realistic estimations of the performances of future devices following technological trends.

The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical phenomena which determine their behaviors. Regarding many emerging non-silicon devices, circuit and system designers very often rely on empirical behavioral macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, and therefore does not allow accurate production quality design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling

a. Advanced Bulk MOSFETs

b. SOI MOSFETs

c. Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, nanosheet MOSFETs, UTB SOI MOSFETs, etc.

d. Junctionless MuGFETs

e. Power and high voltage MOSFETs

2. Junction-based and compound semiconductor FET modeling:

a. Advanced MESFETs

b. Advanced HEMTs

c. III-V and III-N MOSFETs

d. Advanced JFETs

3. Diode and bipolar transistor modeling:

a. Advanced BJTs

b. HBTs

c. IGBTs

d. pn and pin diodes

e. Varactors

4. Emerging transistor modeling:

a. Tunnel FETs

b. Molecular transistors

c. Single Electron Transistors

d. Quantum Dot Transistors

e. Negative Capacitance Transistors

5. Emerging semiconductor devices

Memories, MRAM, PCRAM, etc.

Memristors

Spintronic devices

Layered/2D semiconductor devices

Graphene-based devices

6. TFT

a. a-Si:H TFTs

b. Polycrystalline Si TFTs

c. OTFTs and OECTs

d. Oxide TFTs

e. Single-crystal TFts

7. Modeling of physical effects

a. Noise

b. High frequency operation

c. Cryogenic conditions

d. Mismatch

e. Strain

f. High energy particle interactions in ICs (Cosmic rays and energy beams)

g. ESD events

h. Ballistic and quasi-ballistic transport

i. Layout dependent effects

8. Photonic devices

a. LEDs and OLEDs

b. Photodiodes

c. Solar cells

d. Photodetectors

e. SPADs

f. Photonic Crystals

9. Parameter extraction methods

a. Direct extraction methods

b. Global optimization methods

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please, visit https://ieeeauthorcenter.iece.org/create-your-ieee- article/use-authoring-toolsand-ieee-article-templates/ieee-article-templates/templates-for- transactions/ to download the templates. When submitting your manuscript through the IEEE’s web-based ScholarOne Author Submission and Peer Review System (https://mc.manuscriptcentral.com/jeds), please indicate that your submission is for this special issue.

Guest Editor in Chief:

• Benjamin Iniguez, Universitat Rovira i Virgili, Tarragona, Spain

Guest Associate Editors:

• Yogesh Chauhan, IIT Kanpur (IN) 
• Slobodan Mijalkovic, Silvaco Europe Ltd., St.Ives (UK) 
• Kejfun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
• Jhung-Suk Goo, Global Foundries, Sunnyvale, CA (USA), 
• Marcelo Pavanello, Centro Universitario da FEI, Sao Paulo (BR), 
• Marek Mierzwinski, Keysight Technologies, Santa Rosa, CA (USA)
• Wladek Grabinski, GMC Consulting, Commugny (CH)

Please, direct all communications to Marlene James at m.james@ieee.org

DOI 10.1109/TED.2019.2960953