Talk from W. Grabinski about #compact models at #QuantiAmony #winter #school

Talk from W. Grabinski about #compact models at #QuantiAmony #winter #school. Also very to see that he uses the image (then nice transistor on the yellow page in the middle) made in Device Modeling Group as an example. #cmos #simulations #modelling #semi https://t.co/cqBLzSY2Xq https://t.co/Ry7lH8UThK

— Wladek Grabinski (@wladek60) Feb 28, 2023

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February 28, 2023 at 02:25PM
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[paper] ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Alessandro Ottaviano1, Robert Balas1, Giovanni Bambini2, Antonio del Vecchio2, Maicol Ciani2, Davide Rossi2, Luca Benini1,2 and Andrea Bartolini2

DOI: 10.21203/rs.3.rs-2525734/v1

1 Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, Zurich, 8092, Switzerland.
2 DEI, University of Bologna, Viale Del Risorgimento 2, Bologna, 40136, Italy

Abstract: High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multicore programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multicore cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant’s thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry grade control algorithm under computational-intensive workloads.

• https://github.com/Arm-software/SCP-firmware
• https://github.com/open-power
• https://github.com/pulp-platform/control-pulp 
• https://github.com/openhwgroup/cv32e40p
• https://github.com/pulp-platform/clic
• https://github.com/EEESlab/examon
• https://buildroot.org/

FIG: ControlPULP hardware architecture. On the left, the manager domain with the manager core and surrounding peripherals. On the right, the cluster domain accelerator with the eight cores (workers)

 

[paper] Framework for FPGA Emulation of IC Designs

S. Herbst, G. Rutsch, W. Ecker and M. Horowitz

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

vol. 41, no. 7, pp. 2223-2236, July 2022

DOI: 10.1109/TCAD.2021.3102516

Abstract: This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models. FOSS framework, depicted in Fig. 1, consists of three tools: 1) msdsl ; 2) svreal; and 3) anasymod. All three tools released as open source can be installed either from GitHub or by using the Python package manager (pip).

FIG: Overview of FOSS AMS emulation framework. Analog models are described in Python and compiled into synthesizable SystemVerilog using msdsl, leveraging svreal to implement real-number operations. anasymod then wraps emulator control infrastructure around the DUT and automates EDA tools to produce an FPGA bitstream.

[review] SOI devices and their basic properties

Rudenko, T. E., A. N. Nazarov, and V. S. Lysenko

The advancement of silicon-on-insulator (SOI) devices and their basic properties

Semiconductor Physics, Quantum Electronics & Optoelectronics 23, no. 3 (2020)

DOI: 10.15407/spqeo23.03.227

* V. Lashkaryov Institute of Semiconductor Physics, NAS of Ukraine, 45, prospect Nauky, 03680 Kyiv, Ukraine

Abstract. Silicon-on-insulator (SOI) is the most promising present-day silicon technology. The use of SOI provides significant benefits over traditional bulk silicon technology in fabrication of many integrated circuits (ICs), and in particular, complementary metal-oxide-semiconductor (CMOS) ICs. It also allows extending the miniaturization of CMOS devices into the nanometer region. In this review paper, we briefly describe evolution of SOI technology and its main areas of application. The basic technological methods for fabrication of SOI wafers are presented. The principal advantages of SOI devices over bulk silicon devices are described. The types of SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) and their basic electrical properties are considered. Keywords: silicon-on-insulator (SOI), metal-oxide-semiconductor field-effect transistor (MOSFET), multiple-gate transistor, ultra-thin-body SOI transistor, fully-depleted SOI transistor, interface coupling.

FIG: Equivalent capacitance circuit of the long-channel bulk / PD SOI MOSFET (a), and FD SOI MOSFET (b). Subthreshold characteristics of FD SOI MOSFET and bulk / PD SOI MOSFET (c).

[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea