#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design https://t.co/h6mSqWzJHh #semi https://t.co/u3TDibKq9I
— Wladek Grabinski (@wladek60) Jul 30, 2021
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July 30, 2021 at 06:04PM
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Jul 30, 2021
#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design
from Twitter https://twitter.com/wladek60
July 30, 2021 at 06:04PM
via IFTTT
[special issue] on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems
Guest editorial for the special issue
on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems:
Connecting technologies to applications
Valeria Vadalà, Giovanni Crupi
First published: 27 July 2021; DOI: 10.1002/jnm.2940
REFERENCES:
[1] Cao K-J, Zhang A, Gao J-J. Sensitivity analysis and uncertainty estimation in small-signal modeling for InP HBT (invited paper). Int J Numer Model El. 2021; 34(5): 2851. DOI: 10.1002/jnm.2851
[2] Tang X, Yang T, Jia Y, Xu Y. FW-EM-based approach for scalable small-signal modeling of GaN HEMT with consideration of temperature-dependent resistances. Int J Numer Model El. 2021; 34(5):e2882. DOI: 10.1002/jnm.2882
[3] King JB. Efficient energy-conservative dispersive transistor modelling using discrete-time convolution and artificial neural networks. Int J Numer Model El. 2021; 34(5): 2894. DOI: 10.1002/jnm.2894
[4] Li Y, Mao S, Fu Y, et al. A scalable electrothermal model using a three-dimensional thermal analysis model for GaN-on-diamond high-electron-mobility transistors. Int J Numer Model El. 2021; 34(5):e2875. DOI: 10.1002/jnm.2875
[5] Alim MA, Ali MM, Crupi G. Measurement-based analysis of GaAs HEMT technologies: Multilayer D-H pseudomorphic HEMT versus conventional S-H HEMT. Int J Numer Model El. 2021; 34(5):e2873. DOI: 10.1002/jnm.2873
[6] Osmanoglu S, Ozbay E. From model to low noise amplifier monolithic microwave integrated circuit: 0.03–2.6 GHz plastic quad-flat no-leads packaged Gallium-Nitride low noise amplifier monolithic microwave integrated circuit. Int J Numer Model El. 2021; 34(5):e2859. DOI: 10.1002/jnm.2859
[7] Piacibello A, Costanzo F, Giofré R, et al. Evaluation of a stacked-FET cell for high-frequency applications (invited paper). Int J Numer Model El. 2021; 34(5):e2881. DOI: 10.1002/jnm.2881
[8] Wu M, Cai J, King J, Chen S, Su J, Cao W. Design of a multi-octave power amplifier using broadband load-pull X-parameters. Int J Numer Model El. 2021; 34(5):e2878. DOI: 10.1002/jnm.2878
[9] Abdulbari AA, Abdul Rahim SK, Soh PJ, Dahri MH, Eteng AA, Zeain MY. A review of hybrid couplers: State-of-the-art, applications, design issues and challenges. Int J Numer Model El. 2021; 34(5):e2919. DOI: 10.1002/jnm.2919
[10] Piltyay S, Bulashenko A, Sushko O, Bulashenko O, Demchenko I. Analytical modeling and optimization of new Ku-band tunable square waveguide iris-post polarizer. Int J Numer Model El. 2021; 34(5):e2890. DOI: 10.1002/jnm.2890
[11] Qas Elias BB, Soh PJ, Abdullah Al-Hadi A, Vandenbosch GAE. Design of a compact, wideband, and flexible rhombic antenna using CMA for WBAN/WLAN and 5G applications. Int J Numer Model El. 2020; 34(5):e2841. DOI: 10.1002/jnm.2841
[12] Zhang X, Cunjun R, Dai J, Ding Y, Ullah S, Kosar Fahad A. Design of a reconfigurable antenna based on graphene for terahertz communication. Int J Numer Model El. 2021; 34(5):e2911. DOI: 10.1002/jnm.2911
[13] Gatte MT, Soh PJ, Kadhim RA, Abd HJ, Ahmad RB. Modeling and performance evaluation of antennas coated using monolayer graphene in the millimeter and sub-millimeter wave bands. Int J Numer Model. 2021; 34(5):e2929. DOI: 10.1002/jnm.2929
[14] Xing C, Qi F, Liu Z, Wang Y, Guo S. Terahertz compressive imaging: understanding and improvement by a better strategy for data selection. Int J Numer Model El. 2021; 34(5):e2863. DOI: 10.1002/jnm.2863
Jul 27, 2021
#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers
#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers [ST News https://t.co/BTdQoaGlnA] #semi https://t.co/cgX8Jxqtsy
— Wladek Grabinski (@wladek60) Jul 27, 2021
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[paper] Above Vth Model for SC DG MOSFETs
David Chuyang Hong; Yuan Taur
An Above Threshold Model for Short-Channel DG MOSFETs
in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021
DOI: 10.1109/TED.2021.3092310.
*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA
Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.
Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation
Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.
Jul 26, 2021
[paper] VNWFET Including Tied Compact Model
Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1,
and Abhishek Kumar3
3D Logic Cells Design and Results Based on Vertical NWFET Technology
Including Tied Compact Model
In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.
DOI: 10.1007/978-3-030-81641-4_14
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan
Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.
Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)
Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).
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