Jun 28, 2021

Program 2021: Symposium on Schottky Barrier MOS Devices

The symposium goal is to combine the activities of an enthusiastic group of Schottky barrier researchers worldwide. The topics cover all important aspects of potential applications, simulation and modeling, processing and implementation for CMOS/SOI technologies, Quantum technologies and approaches for neuromorphic applications. The content will be beneficial for anyone who needs to learn the opportunities and challenges of this technology since the first introduction by Walter Schottky in the 1938s. New aspects and future proposals to make the Schottky barrier into the main stream are welcome.

Wed 30.06.2021 (Virtual)
13:00-13:05  
Opening IEEE DL
13:05-14:00














IEEE Distinguished Lecture: Tunneling Graphene FET
Gana Nath Dash, Sambalpur University (IN)
Abstract: During the last few decades, aggressive scaling in Si MOSFET
(Metal Oxide Semiconductor Field Effect Transistor) architecture has
given rise to several short channel effects, which in turn has set a performance
limit on the device owing to constraint in Si technology. The emergence of
graphene at this juncture with a host of exotic and favorable electronic
properties, generated new hopes for the FET industry. While the graphene
based analogue FET witnessed some advantages, the digital counterpart
showed a dismal performance, primarily due to the zero bandgap of graphene
(poor ON/OFF ratio). For a way out, an alternative architecture based on the
quantum tunneling process is augmented with the graphene FET resulting
in the new device named TGFET.

14:00-14:05  
Opening SSBMOS
14:05-14:35   


















Germanium nanosheet and nanowire transistor technologies for beyond
CMOS applications

Walter M. Weber, Raphael Böckle, Lukas Wind, Kilian Eysin, Daniele Nazzari,
Tatli Ezgi, Oliver Solfronk, Alois Lugstein and Masiar Sistani,
Institute of Solid State Electronics, TU Vienna (A)
Abstract: The ultimate downscaling limits of conventional field effect transistors
calls for alternative computational methods that provide perspectives towards the
enhancement of computational complexity, circuit performance and energy
efficiency. In this sense germanium nano-transistors offer both an approachable
access to quantum confinement effects and promising electronic transport properties
that distinctly are compatible with modern CMOS fabrication flows. We will discuss
the applicability of different germanium active regions and gating architectures
towards the realization of computational electronics with added functionality.
On top of exploring different realizations of reconfigurable transistors with
programmable polarity we will discuss further functionality enhancement by
enabling operability within the negative differential resistance regime at room
temperature. Prospective implications at the circuit level will be discussed.
14:40-15:10





  
Evolving contact-controlled thin-film transistors
Radu Sporea, University of Surrey (UK)

Abstract: TFT designs that comprise multiple gates and rectifying source contacts
can be designed to produce linear transconductance and act as robust amplifiers
and signal converters. This talk outlines device design and opportunities in
emerging edge processing applications.
15:10-15:50   COFFEE BREAK
15:50-16:20













  
Compact Modelling of Dually-Gated Reconfigurable Field-Effect Transistors
Christian Römer*, Ghader Darbandy*, Mike Schwarz*, Jens Trommer**,
André Heinzig**, Thomas Mikolajick**, Walter M. Weber***, Benjamín
Iñíguez**** and Alexander Kloes*
*NanoP, THM (DE), **namLAB, TU Dresden (DE),
***TU Vienna (A), ****DEEEA, URV (ES)

Abstract: This work presents a closed-form and physics-based DC compact model,
which is applicable on dually-gated reconfigurable field-effect transistors (RFETs).
The presented compact model is focused on the charge-carrier injection at the
device’s source and drain side Schottky barriers, which can be separated into field
emission and thermionic emission current contributions. This work explains the basic
equations which are used to calculate the current contributions and shows calculated
device characteristics compared to measurements.

16:25-16:55









  
The Schottky barrier transistor in all its forms
Laurie Calvet*, John P. Snyder**, Mike Schwarz***
*C2N, University Paris (FR),** JCap, LLC (USA), ***NanoP, THM (DE)

Abstract: The Schottky barrier (SB) transistor, where the source and drain of a
conventional planar MOSFET are replaced with metallic contacts, was first
explored in the 1960s. Since then, many variations on this structure have been
explored in the literature including: different semiconductors materials such as
other non-organic semiconductors and nano-structures such as carbon nanotubes
and nanowires. In this talk we review some of the changes in the electronic transport
that are observed as the geometry and materials of the SB transistors are changed.

Jun 26, 2021

Ten Lessons Learned from Andy Grove [Semiwiki https://t.co/ePZ5MMBbeO] #semi https://t.co/wc8oJZVA5R



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June 26, 2021 at 12:39PM
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Jun 25, 2021

[paper] Accelerated numerical modeling of RF circuits

Hongliang Li1, Jian-Ming Jin1, Amir Hajiaboli2, Douglas R. Jachowski2
Accelerated numerical modeling of RF circuits using network characteristic mode analysis
Int J Numer Model. 2021;e2898 pp.1-16
DOI: 10.1002/jnm.2898

1 Center for Computational Electromagnetics, Department of Electrical and Computer Engineering, University of Illinois, USA
2 Resonant Inc., Goleta, California, USA


Abstract: A fast numerical modeling approach based on network characteristic mode analysis (CMA) is presented and investigated for analyzing electrical layouts in miniature RF filters, such as surface acoustic wave filters. In this approach, a generalized eigenvalue decomposition is performed on the Z-parameters of an electrical layout at one or two sampling frequencies that can be computed and extracted with any numerical full-wave method. The obtained eigenvalues are used to extract modal resistance, inductance, and capacitance matrices for each eigenmode. The frequency dependence of the modal resistance matrix can be assumed a priori or determined automatically, and the modal inductance and capacitance matrices are assumed frequency independent. These modal matrices are then used to approximate the Z-parameters at any other frequencies to provide the response of the electrical layout, which can then be combined with the frequency responses of other components, such as resonators, to yield the electrical response of an entire RF filter. Compared with the previously developed analytic extension of eigenvalues, this fast CMA-based method is less affected by the frequency variation of eigenmodes since the frequency dependencies of the eigenmodes are implicitly canceled out in its formulation. The accuracy of this approach is evaluated by comparing with results from full-wave analyses. For RF circuits whose electrical sizes are small and whose frequency range of interest is relatively small, the proposed CMA- based fast frequency sweep approach is found to be sufficiently accurate and highly practical for engineering applications.

Fig: Configuration of a four-port microstrip circuit with two lumped devices 
(A) Dimensions of the layout; (B) Equivalent circuit for a bandpass filter; 
(C) Equivalent circuit for the Schottky diode

Acknowledgements: The third and fourth authors would like to thank Andy Guyette and Jackson Massey from Resonant, Inc. for useful discussions and help in some of the simulations presented in this article.


[paper] Nanosheet field effect transistors

J. Ajayana, D. Nirmalb, Shubham Tayala, Sandip Bhattacharyaa, L. Arivazhaganc, A.S. Augustine Fletcherb, P. Murugapandiyand, D. Ajithae
Nanosheet field effect transistors - A next generation device to keep Moore’s law alive:
An intensive study
Microelectronics Journal 114 (2021) 105141
DOI: 10.1016/j.mejo.2021.105141

a SR University, Warangal, Telangana, India
b Karunya Institute of Technology and Sciences, Coimbatore, Tamilnadu, India
c Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India
d Anil Neerukonda Institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India
e Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, India


Abstract: Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which limits their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7nm to 5nm. However, further shrinking of feature size to 3nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate material effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore’s Law alive.

Fig: 3-D views of (a) FinFET (b) stacked NW-FET (c) vertically stacked NSFET.















#Shenzhen Technology #University sets up school of #IC with Chinese #SMIC



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June 25, 2021 at 02:09PM
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