Sep 2, 2024

[mos-ak] MOS-AK/ESSERC Workshop in Bruges (B) September 9, 2024

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK/ESSERC Workshop in Bruges (B)
September 9, 2024

Scheduled consecutive 21st MOS-AK/ESSDERC SPICE/Compact Modeling Workshop organized in Bruges, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in OpenPDKs. The MOS-AK workshop program is available online

It will be followed by ESSERC W13 Workshop "The Future of CMOS: Building an Infrastructure to Fill the Gap with the VLSI Design Research Ecosystem", which will link the W13 workshop to the pathfinding PDK as an important tool to enable interaction within the academic research ecosystem. The workshop would end with a panel discussion where the different speakers can exchange their views on how to build the proper infrastructure for this evolution. The W13/ESSERC workshop program is available online:

Our industrial partner is organizing a complementary Keysight Device Modeling Connect Seminar. The seminar program available online

-- W.Grabinski on the behalf of International MOS-AK Committee

Enabling Compact Modeling R&D Exchange

WG010924


Jul 23, 2024

[mos-ak] [upcoming events] MOS-AK workshop series

The MOS-AK Association continue SPICE modeling discussions and its standardization efforts by organizing future compact modeling meetings, workshops and panels around the globe thru the 2024 Year, including:
-- W.Grabinski on the behalf of the International MOS-AK Committee

Enabling Compact Modeling R&D Exchange

23072024

Jul 22, 2024

[open letter] EU must keep funding free software

Initially published by petites singularités. English translation provided by OW2.

Since 2020, Next Generation Internet (NGI) programmes, part of European Commission’s Horizon programme, fund free software in Europe using a cascade funding mechanism (see for example NLnet’s calls). This year, according to the Horizon Europe working draft detailing funding programmes for 2025, we notice that Next Generation Internet is not mentioned any more as part of Cluster 4.

NGI programmes have shown their strength and importance to supporting the European software infrastructure, as a generic funding instrument to fund digital commons and ensure their long-term sustainability. We find this transformation incomprehensible, moreover when NGI has proven efficient and economical to support free software as a whole, from the smallest to the most established initiatives. This ecosystem diversity backs the strength of European technological innovation, and maintaining the NGI initiative to provide structural support to software projects at the heart of worldwide innovation is key to enforce the sovereignty of a European infrastructure. Contrary to common perception, technical innovations often originate from European rather than North American programming communities, and are mostly initiated by small-scaled organizations.

Previous Cluster 4 allocated 27 million euros to:
  • “Human centric Internet aligned with values and principles commonly shared in Europe” ;
  • “A flourishing internet, based on common building blocks created within NGI, that enables better control of our digital life” ;
  • “A structured ecosystem of talented contributors driving the creation of new internet commons and the evolution of existing internet commons”.
In the name of these challenges, more than 500 projects received NGI funding in the first 5 years, backed by 18 organisations managing these European funding consortia.

NGI contributes to a vast ecosystem, as most of its budget is allocated to fund third parties by the means of open calls, to structure commons that cover the whole Internet scope - from hardware to application, operating systems, digital identities or data traffic supervision. This third-party funding is not renewed in the current program, leaving many projects short on resources for research and innovation in Europe.

Moreover, NGI allows exchanges and collaborations across all the Euro zone countries as well as “widening countries”1, currently both a success and an ongoing progress, likewise the Erasmus programme before us.  NGI is also an initiative that contributes to the opening and maintenance of relationships over a longer period of time than project financing. It encourages implementing projects funded as pilots, backing collaboration, identification and reuse of common elements across projects, interoperability in identification systems and beyond, and setting up development models that mix diverse scales and types of European funding schemes.

While the USA, China or Russia deploy huge public and private resources to develop software and infrastructure that massively capture private consumer data, the EU can’t afford this renunciation. Free and open source software, as supported by NGI since 2020, is by design the opposite of potential vectors for foreign interference. It lets us keep our data local and favors a community-wide economy and know-how, while allowing an international collaboration. This is all the more essential in the current geopolitical context: the challenge of technological sovereignty is central, and free software allows addressing it while acting for peace and sovereignty in the digital world as a whole.

Original text and list of signatories: https://pad.public.cat/lettre-NCP-NGI#

REF:
[1] As defined by Horizon Europe, widening Member States are Bulgaria, Croatia, Cyprus, the Czech Republic, Estonia, Greece, Hungary, Latvia, Lituania, Malta, Poland, Portugal, Romania, Slovakia and Slovenia. Widening associated countries (under condition of an association agreement) include Albania, Armenia, Bosnia, Feroe Islands, Georgia, Kosovo, Moldavia, Montenegro, Morocco, North Macedonia, Serbia, Tunisia, Turkey and Ukraine. Widening overseas regions are: Guadeloupe, French Guyana, Martinique, Reunion Island, Mayotte, Saint-Martin, The Azores, Madeira, the Canary Islands.

Jul 4, 2024

[paper] anybody can design and build a chip

Krzysztof Herman, Norbert Herfurth, Tim Henkes, Sergei Andreev, Rene Scholz, Markus Müller, Mario Krattenmacher, Harald Pretl, and Wladyslaw Grabinski
On the Versatility of the IHP BiCMOS Open Source and Manufacturable PDK: 
A step towards the future where anybody can design and build a chip
IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 30-38, Spring 2024
DOI: 10.1109/MSSC.2024.3372907

Abstract: In this article, we introduce the first European open source process design kit (PDK), namely IHP-Open130-G2. We provide a concise history of the PDK itself and offer a brief comparison with some alternative open source PDKs, such as SKY130 and GF180MCU. The article also includes a process description and details on deliverables, offering insights into available devices, models, supported open source tools, and workflows. As the IHP-Open130-G2 is currently under development, we present key points outlining future activities. This aims to inform and attract users to join the open source silicon community. The concluding section of the article compares measurement results for active devices with compact model results. The article concludes with a cryptographic Internet protocol (IP) core based on IHP-Open130-G2 as an exemplary use case.

FIG: Silicon Proven Application: The final layout of the HEP custom cryptographic IP core.

[REF] “130nm BiCMOS open source PDK, dedicated for analog, mixed signal and RF design.” GitHub. Online: https://github.com/IHP-GmbH/IHP-Open-PDK

Jul 3, 2024

[paper] 5-DC-Parameter MOSFET Model

Deni Germano Alves Neto 1,3, Mohamedkhalil Bouchoucha 2,3, Gabriel Maranhão 1, Manuel J. Barragan 3, Márcio Cherem Schneider 1, Andreia Cathelin 2, Sylvain Bourdel 1
and Carlos Galup-Montoro 1
Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model
IEEE Access; vol. 12 (2024)
DOI: 10.1109/ACCESS.2024.3417316

1 Department of Electrical and Electronics Engineering, FUSC, Florianópolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)

Abstract: This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4GHzlow-noise-amplifier in a 28nm FD-SOI CMOS technology. Obtained results in terms of S11, S21, NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.
 
Technology 130nm28nm
Transistor NMOS PMOS NMOS PMOS
W/L (um/um)
VTO (mV)
10/0.12
490
10/0.12
-478
1/0.06
389
1/0.06
-404
Is (uA)11.78 9.39 3.15 0.76
n1.41 1.46 1.15 1.01
σ0.053 0.048 0.018 0.029
ς0.007 0.031 0.039 0.024
δ- - 0.079 -0.076

FIG:  Conceptual structure of the ACM2 Model and its 6-DC parameters.

Acknowledgment: The authors would like to thank the STIC-AmSud multi national cooperative scientific program for supporting this research and STMicroelectonics and the Institute for High-Performance Microelectronics (IHP) for the design kits and silicon measurements. This work was supported in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (BR); in part by the Conselho Nacional de Desenvolvimento Científico e Tecnológico, (BR); in part by the TIMA Laboratory, Grenoble (F) and in part by STMicroelectronics, Crolles, France.