Sedemos News

Feb 9, 2023

#Wolfspeed to Build 200-mm #SiC #Wafer #Fab in Germany

#Wolfspeed to Build 200-mm #SiC #Wafer #Fab in Germany https://t.co/WZIzzETJ44 #semi https://t.co/RY58nMQ2B1
— Wladek Grabinski (@wladek60) Feb 9, 2023

from Twitter https://twitter.com/wladek60

February 09, 2023 at 08:46PM
via IFTTT

[Compact Model Coalition] Advanced SPICE model for ESD diodes https://t.co/n83vRcQhhK #semi https://t.co/PIuhcqVLw2

[Compact Model Coalition] Advanced SPICE model for ESD diodes https://t.co/n83vRcQhhK #semi https://t.co/PIuhcqVLw2
— Wladek Grabinski (@wladek60) Feb 9, 2023

from Twitter https://twitter.com/wladek60

February 09, 2023 at 06:07PM
via IFTTT

[C4P] RISC-V Summit Europe

On 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing.

The event will include a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research including technology demonstrations and poster sessions.

RISC-V Summit Europe is an opportunity not to be missed, come to Barcelona from 5-9th June 2023 to be part of the new wave of European computing innovation!

Call for Submissions

RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across the European RISC-V ecosystem. Attendees from academia, research, SMEs, industry, and open source communities will come together to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing in Europe.

The event will have a single track of keynotes, invited and selected talks alongside an exhibition showcasing the latest developments across industry and research, including technology demonstrations and poster sessions. We invite blind submissions related to RISC-V addressing the following technical topics of interest:

    Automotive
    Cloud computing
    Compilation and code optimization
    Embedded systems, IoT, edge computing
    Hardware/software co-design
    High-performance computing
    Open EDA tools
    Open-source hardware and open silicon
    Operating system and software ecosystem
    RISC-V related educational activities
    RISC-V ISA extensions
    Systems-on-Chip, including processor cores, accelerators, peripherals
    Security and functional safety
    Verification
    Any other topic related to RISC-V and open hardware

We also welcome non-blind submissions related to:

    Commercial applications for real world deployment
    Policies, strategies, business and industry trends
    Publicly funded projects presentations and/or results

Important dates:

    Abstract submissions hard deadline: Monday, March 13th, 2023, AOE.
    Author notifications: Monday, April 24th, 2023, AOE.
    Final abstract version, de-anonymized, deadline: Thursday, Monday May 1st, 2023, AOE.
    Final slides and poster deadline: Thursday, June 1st, 2023, AOE.
    RISC-V Summit Europe: 5-9 June, 2023, Barcelona.

[Hisayo Momose] My Journey as a Researcher in the Semiconductor Field

graphical user interface, text, application

Hisayo Mosmose's Story

Read Hisayo Momose's article from the IEEE EDS January Newsletter, "My Journey as a Researcher in the Semiconductor Field."

Dr. Momose has more than 30 years of experience in research and development at Toshiba Corporation, Japan. She is a recipient of several awards and honors, and has authored or co-authored nearly 200 papers published in technical journals and conference proceedings [read more...]

#IEEE #EDS #ElectronDevices #WiEDS #womeinengineering #semiconductors

Feb 8, 2023

[paper] OpenSpike: An OpenRAM SNN Accelerator

Farhad Modaresi¹, Matthew Guthaus², and Jason K. Eshraghian³
OpenSpike: An OpenRAM SNN Accelerator
arXiv:2302.01015v1 [cs.AR] 2 Feb 2023

1) Dept. of Electrical Engineering Allameh Mohaddes Nouri University Nur, Mazandaran, Iran
2) Dept. of Computer Science and Engineering, UC Santa Cruz Santa Cruz, CA, United States
3) Dept. of Electrical and Computer Engineering, UC Santa Cruz Santa Cruz, CA, United States

Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.

The design is open sourced and available online: https://github.com/sfmth/OpenSpike

Fig: OpenSpike core - system architecture and data flow