Sedemos News

Nov 2, 2020

#TSMC to Build Fab in #Arizona and They are #Hiring! https://t.co/AtMOY6j3ox #semi https://t.co/zfWFCKx3JT

#TSMC to Build Fab in #Arizona and They are #Hiring! https://t.co/AtMOY6j3ox #semi pic.twitter.com/zfWFCKx3JT
— Wladek Grabinski (@wladek60) November 2, 2020

from Twitter https://twitter.com/wladek60

November 02, 2020 at 11:22AM
via IFTTT

Oct 30, 2020

Video Tutorial: What is Verilog-A

Verilog-A is a behavioural modelling language for analog circuits from the Verilog Family. It is the subset of Verilog-AMS. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification. The intent of Verilog-A HDL is to let designers of analog systems and integrated circuits create and use modules that encapsulate high-level behavioural descriptions as well as structural descriptions of systems and components.

Reference:

[1] OVI Verilog-A LRM , 1996
[2] https://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf
[3] A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015
[4] https://github.com/cogenda/VA-BSIM48/blob/master/bsim4_release.va

[PhD Thesis] III-V MOS-HEMTs for 100-340GHz Communications Systems

UNIVERSITY OF CALIFORNIA

Santa Barbara

III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems

A dissertation for PhD degree in Electrical and Computer Engineering

by Brian David Markman

Abstract: This work summarizes the efforts made to extend the current gain cutoff frequency of InP based FET technologies beyond 1THz. Incorporation of a metal-oxide-semiconductor field effect transistor (MOSFET) at the intrinsic Gate Insulator-Channel interface of a standard high electron mobility transistor (HEMT) has enabled increased g_m,i by increasing the gate insulator capacitance density for a given gate current leakage density. Reduction of RS,TLM from 110 Ω.μm to 75Ω.μm and Ron(0) from 160Ω.μm to 120Ω.μm was achieved by removing/thinning the wide bandgap modulation doped link regions beneath the highly doped contact layers. Process repeatability was improved by developing a gate metal first process and D_it was improved by inclusion of a post-metal H₂ anneal. In_xGa_1-xAs / InAs composite quantum wells clad with both InP and In_xAl_1-xAs were developed for high charge density and low sheet resistance to minimize source resistance.

Figure a) InP-based HEMT b) III-V DC optimized MOSFET c) proposed InP-based MOS-HEMT

[Citation] Markman, B. D. (2020). III-V In_xGa_1-xAs / InP MOS-HEMTs for 100-340GHz Communications Systems. UC Santa Barbara. ProQuest ID: Markman_ucsb_0035D_14853. Merritt ID: ark:/13030/m5v4681j. Retrieved from https://escholarship.org/uc/item/6st812pb

Oct 29, 2020

#Congratulations to Dr. Arokia Nathan J.J. Ebers Award winner

#Congratulations to 2020 #IEEE #ElectronDevicesSociety J.J. Ebers Award winner, Dr. Arokia Nathan @IEEEorg @IEEEAwards @Cambridge_Uni #semi https://t.co/zQ5YIDm3wl
— Wladek Grabinski (@wladek60) October 29, 2020

from Twitter https://twitter.com/wladek60

October 29, 2020 at 08:49AM
via IFTTT

Fwd: Patrick Fay DL - III-N Nanowire FETs for Low-Power Applications

Patrick Fay DL - III-N Nanowire FETs for Low-Power Application

The EDS Germany Chapter and NanoP proudly presents Patrick Fay from University of Notre Dame, Indiana, USA
for a Distinguished Lecture on "III-N Nanowire FETs for Low-Power Applications". The lecture will be held on
23th November 2020 at 3pm Berlin time. To view complete details for this event, click here to view the announcement