A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2

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Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper

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#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei https://t.co/748KTEgqk7

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[paper] Design techniques for low-voltage analog integrated circuits

Matej Rakus, Viera Stopjakova, Daniel Arbet

Institute of Electronics and Photonics, Faculty of Electrical Engineering

and Information Technology Slovak University of Technology in Bratislava, Slovakia,

Journal of ELECTRICAL ENGINEERING, Vol.68 (2017), No.4, 245–255

DOI: 10.1515/jee-2017–0036

ABSTRACT: In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

Fig: Parameter gm/ID versus the normalized drain current. MOS transistor operates in weak inversion (WI) for i_c < 0.1. Strong inversion (SI) is for i_c < 10. Everything in between belongs to the moderate inversion (MI) with center in i_c = 1