[mos-ak] [Final Program] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    Final Workshop Program 

 
Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

• Preannouncement - Sept. 2016
  
• Call for Papers - Oct. 2016
  
• Final Workshop Program - Nov. 2016
  
• MOS-AK Workshop - Dec. 7 2016
•   9:00-12:00 Morning Session
• 13:00-16:00 Afternoon Session

Venue:

540 Cory Hall 
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also http://www.eecs.berkeley.edu/Directions/

Final MOS-AK/Berkeley Workshop Program Online 

http://www.mos-ak.org/berkeley_2016/

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG10112016

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[mos-ak] [press note] 14th MOS-AK ESSDERC/ESSCIRC Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

14th MOS-AK ESSDERC/ESSCIRC Workshop

Lausanne, September 12, 2016

The MOS-AK Modeling Working Group, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual autumn workshop on September 12, 2016 in Lausanne (CH) as its 14th consecutive modeling event at the ESSDERC/ESSCIRC Conference. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by ASCENT Network (lead sponsor) and EPFL EDLab, with technical program sponsorship provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of nanoHUB.org.

 

A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. 

 

The workshop was opened by Prof. J. Greer; Tyndall National Institute, the MOS-AK keynote speaker, who has introduced the ASCENT Network. The ASCENT is combined resources of Tyndall (Ireland), imec (Belgium) and Leti (France) nanofabrication capabilities and electrical characterization facilities integrated into a single research infrastructure present a truly unique R&D opportunity. It provides characterization community with access to advanced test chips, flexible fabrication and advanced test and characterization equipment to accelerate development of advanced models at scales of 14nm and below.

 

The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were delivered by leading academic and industrial experts, including: Denis Rideau; STM (F), presenting a modeling study of the drain current in advanced MOSFETs. Maria-Alexandra Paun; EPFL (CH), focusing on the humidity sensors based on MWCNTs/MMA composite in SOI CMOS technological process. Mike Brinson; London Met (UK), presenting QUCS-S - maturing GPL software package for circuit simulation and compact modeling of current and emerging technology devices. Alexander Kloes; THM Giessen (D), discussing a closed-form charge-based current model of organic TFT including non-linear injection effects. Jean-Michel Sallese; EPFL (CH), discussing an advances in analytical modeling. Marco Bellini, ABB CRC (CH), presenting extraction of compact models for EMI / EMC simulations of power devices. Muhammad Nawaz; ABB CRC (S), reviewed characterization and modeling of SiC MOSFET power modules. Mansun Chan; HKUST (HK), discussing concurrent device and circuit reliability simulation. Benjamin Iñiguez; URV (SP), talking about temperature dependent GIZO TFT modeling. Mike Schwarz; THM (D), discussing analytical III-V SB MOSFET modeling and its performance analysis from room to cryogenic temperature. Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at http://www.mos-ak.org/lausanne_2016

 

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2016/2017 including:

* 9th International MOS-AK Workshop at Berkeley in the timeframe of IEDM and CMC meetings (Dec.7, 2016) 

* Spring MOS-AK Workshop in Lausanne during DATE Conference (March 31 2017)

* 2nd Sino MOS-AK Workshop in Hangzhou (June 2017)

* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)

 

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.

 

About ASCENT Network:

ASCENT provides fast and easy access to the world's most advanced CMOS technologies and infrastructure including access to 14nm CMOS device data, nanoscale test chips and device characterisation facilities at Tyndall (Ireland), imec (Belgium) and Leti (France). ASCENT has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 654384.

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[paper] Field programmable analog array: A boon for analog world

Field programmable analog array: A boon for analog world

Dipti and B. V. R. Reddy,

2016 3rd International Conference on Computing for Sustainable Global Development 

(INDIACom), New Delhi, India, 2016, pp. 2975-2980.

Abstract: n analog chips designing, fabricating, and testing takes a lot of time, money and perfection. In contrast design of digital integrated circuits is fully automated now a day. Due to simpler nature of digital circuits, as compared to Analog circuits, leads to development of libraries and synthesis tools for fast synthesis of digital circuits. To reduce the cost and time-to-market CPLDs and FPGAs are generally used for prototyping of digital integrated circuits. But FPAAs i.e Field Programmable Analog Arrays are boon for designing of analog and mixed-signal Integrated Circuits because of rapid prototyping. FPAA is not only optimal for all solution in contrast to FPGAs but it also reduces the verification and designing cost. This again results from complex nature of analog circuits which needs factors like signal to noise ratio, bandwidth, frequency response, linearity etc. to be addressed. FPAAs are made using configurable analog blocks (CAB) and networks, which are used to provide required interconnection among Cabs. Like FPGAs, circuit functionality is much more sensitive to parasitics introduced by the programming devices in FPAA. So the design of FPAAs architecture and CABs are mutually dependent. To design an efficient FPAA, a designer needs to compromise between flexibility and the number of programmable switches in designing FPAA architectures and the CAB topologies. Various papers are studied for different topologies used in FPAAs and various applications designed with the use of FPAA. In March 2013, Paul Hasler come up with automated approach based on EKV model for characterization of device mismatch, second order defects with temperature. After verification of characterization current sources were created with 2.2% RMS error over dynamic range of 25dB. Field programmable gate array represents a new direction to analog and mixed signal domain keeping the idea of FPGAs in digital domain. RASP is useful for analog designers because they can save the analog components in the form of CABs. RASPER tool was developed for placement and routing of RASP 2.7 and RASP 2.8 versions Whereas GRASPER was developed for RASP 2.9.In digital circuits parasitic only affect the speed of operation but in analog circuits they plays a crucial role for circuit performance and functionality. Floating gate technology was used to simplify designing and implementation, increased system reliability, high precision, innovative approach. In near future FPAA technology will come up with better architecture, low power and more applications with less time to market.

keywords: Decision support systems, Handheld computers, Configurable analog block (CAB), Field programmable analog array (FPAA), Generic reconfigurable array specification and programming environment tool (GRASPER), Operational Transconductance Amplifier, Reconfigurable analog signal processor (RASP)

[read more...]

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU

— Wladek Grabinski (@wladek60) October 27, 2016

from Twitter https://twitter.com/wladek60

October 27, 2016 at 05:08PM
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