Nov 7, 2016

[paper] Field programmable analog array: A boon for analog world

Field programmable analog array: A boon for analog world
Dipti and B. V. R. Reddy,
2016 3rd International Conference on Computing for Sustainable Global Development 
(INDIACom), New Delhi, India, 2016, pp. 2975-2980.

Abstract: n analog chips designing, fabricating, and testing takes a lot of time, money and perfection. In contrast design of digital integrated circuits is fully automated now a day. Due to simpler nature of digital circuits, as compared to Analog circuits, leads to development of libraries and synthesis tools for fast synthesis of digital circuits. To reduce the cost and time-to-market CPLDs and FPGAs are generally used for prototyping of digital integrated circuits. But FPAAs i.e Field Programmable Analog Arrays are boon for designing of analog and mixed-signal Integrated Circuits because of rapid prototyping. FPAA is not only optimal for all solution in contrast to FPGAs but it also reduces the verification and designing cost. This again results from complex nature of analog circuits which needs factors like signal to noise ratio, bandwidth, frequency response, linearity etc. to be addressed. FPAAs are made using configurable analog blocks (CAB) and networks, which are used to provide required interconnection among Cabs. Like FPGAs, circuit functionality is much more sensitive to parasitics introduced by the programming devices in FPAA. So the design of FPAAs architecture and CABs are mutually dependent. To design an efficient FPAA, a designer needs to compromise between flexibility and the number of programmable switches in designing FPAA architectures and the CAB topologies. Various papers are studied for different topologies used in FPAAs and various applications designed with the use of FPAA. In March 2013, Paul Hasler come up with automated approach based on EKV model for characterization of device mismatch, second order defects with temperature. After verification of characterization current sources were created with 2.2% RMS error over dynamic range of 25dB. Field programmable gate array represents a new direction to analog and mixed signal domain keeping the idea of FPGAs in digital domain. RASP is useful for analog designers because they can save the analog components in the form of CABs. RASPER tool was developed for placement and routing of RASP 2.7 and RASP 2.8 versions Whereas GRASPER was developed for RASP 2.9.In digital circuits parasitic only affect the speed of operation but in analog circuits they plays a crucial role for circuit performance and functionality. Floating gate technology was used to simplify designing and implementation, increased system reliability, high precision, innovative approach. In near future FPAA technology will come up with better architecture, low power and more applications with less time to market.

keywords: Decision support systems, Handheld computers, Configurable analog block (CAB), Field programmable analog array (FPAA), Generic reconfigurable array specification and programming environment tool (GRASPER), Operational Transconductance Amplifier, Reconfigurable analog signal processor (RASP)

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Oct 27, 2016

2017 1st Electron Devices Technology and Manufacturing Conference (call for #papers) https://t.co/CAj9B5ifWU


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October 27, 2016 at 05:08PM
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AMS Multi Project Wafer Service

AMS MPW Service:

ams' Multi Project Wafer (MPW) service, also known as shuttle runs, is a fast and cost-efficient prototyping service, which combines several designs from different customers onto a single wafer.

ams’ best in class MPW service offers significant cost advantages for foundry customers as the costs for wafers and masks are shared among a number of different shuttle participants. It includes the whole range of 0.18µm and 0.35µm specialty processes:
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The complete MPW schedule including detailed start dates per process is available on the web at http://asic.ams.com/MPW

Deliverables: Participating the ams MPW service includes the delivery of 40 prototypes for design verification. Packaged engineering samples are offered within 2 days (ceramic) and 3 weeks (plastics) cycle time, respectively. The total turnaround time from MPW deadline to delivery is app. 8 weeks (CMOS). Overall, ams offers almost 150 MPW start dates in 2016 and 2017, enabled by long lasting co-operations with partner organizations such as CMP, Europractice, Fraunhofer IIS and Mosis. Customers located in APAC region may also participate via our local MPW program partners Toppan Technical Design Center Co., Ltd (TDC) and MEDs Technologies [read more...]

ARM Fellow Surveys Moore's Law at 3nm IC https://t.co/JUPsAtrkFb #papers


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Oct 26, 2016

[JEDS #papers ] Characterization of RF Noise in UTBB FD-SOI MOSFET https://t.co/LNlvvNOb5V https://t.co/XQsatKslTX


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