Showing posts with label floating p (FP)- layer. Show all posts
Showing posts with label floating p (FP)- layer. Show all posts

Jul 22, 2020

[paper] Thyristor Conduction-Insulated Gate Bipolar Transistor

Mengxuan Jiang1 (Member, IEEE) and Longjiang Gao1
Simulation Study of a Thyristor Conduction-Insulated Gate Bipolar Transistor (TC-IGBT) 
with a p-n-p Base and an n-p-n Collector for Reducing Turn-Off Loss," 
IEEE TED, vol. 67, no. 7, pp. 2854-2858, July 2020
DOI: 10.1109/TED.2020.2995343
1School of Electrical Engineering, Chongqing University, Chongqing 400044, China

Abstract: This article proposes a thyristor conduction-insulated gate bipolar transistor (TC-IGBT) with a p-n-p base and an n-p-n collector to reduce turn-off loss. The parasitic p-collector/n-drift/floating p (FP)-layer/carrier stored (CS)-layer thyristor is activated by the double channel gate and the p-n-p base acts a hole barrier to increase hole concentration at the top side. The n-p-n collector is used for extracting electrons from the n-drift region to decrease hole concentration at the bottom side. Therefore, these two effects form linear and descending hole concentration distribution profile. As a result, the p-n-p base and the n-p-n collector in the TC-IGBT offers lower turn-off loss and turn-off fall time. TCAD numerical simulations show reductions up to 47% (3.15 mJ) and 52% (34 ns) in turn-off loss and turn-off fall time, respectively, when compared to a field stop (FS) IGBT with similar breakdown voltage, threshold voltage, and short circuit time. Therefore, this designed structure may be attractive for power electronics applications.
Fig: (a) Proposed TC-IGBT and (b) its equivalent circuit model

Acknowledgment: This work was supported in part by the National Natural Science Foundation of China under Grant 51707025 and in part by the Chinese Universities Scientific Fund under Grant 106112017 CDJXY150099.