Lihua Xu, Kaifei Chen, Zhi Li, Yue Zhao, Lingfei Wang and Ling LiPhysics-Based
Compact Model of Independent Dual-Gate BEOL-Transistors
for Reliable Capacitorless Memory
in IEEE Journal of the Electron Devices Society
DOI: 10.1109/JEDS.2024.3393418
School of Microelectronics, University of Science and Technology of China, Hefei (CN)
State Key Lab of FTIC, Institute of Microelectronics of Chinese Academy of Sciences, Beijing (CN)
University of Chinese Academy of Sciences, Beijing (CN)
Abstract: Capacitorless DRAM architectures based on Back End-of-Line (BEOL)-transistors are promising for long retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to ~ 50 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.
Fig: (a) Schematic illustration of the IDG a-IGZO FETs with a thickness of ~5nm. (b) Agreement between analytical and numerical results of back gate surface potentials at different VDS with errors in the inset. VTG & VBG denotes DG synchronized-sweep with the same voltage.
Acknowledgements: This work was supported in part by National key research and development program (Grant Nos. 2021YFB3600704), the National Natural Science Foundation of China (Grant Nos. 62274178, 92264204), CAS Interdisciplinary Innovation Team [JCTD-2022-07].
