Let’s get back to the business of building microchips in America

[https://t.co/UiC0Uc61OM] Gina Raimondo: “Let’s get back to the business of building microchips in America” #semi https://t.co/GuMK2hWVKj

— Wladek Grabinski (@wladek60) Mar 7, 2022

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March 07, 2022 at 09:07AM
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[mos-ak] Re: MOS-AK/Guangzhou // Q1 2022 MOS-AK Panel: Compact Model Verilog-A standardization and implementation

On Fri, Feb 25, 2022 at 9:18 AM zhang@xmodtech.cn <zhang@xmodtech.cn> wrote:

Dear Wladek,

we will hold MOS-AK guangzhou event in August, 11-12th.  two days.  10th. August can be used for one day training. 

Now, we come to the invited talk, have you good candidate for this year event?

thanks for your email and update on MOS-AK/Guangzhou workshop planning.

We have organized MOS-AK panel dedicated to the compact model Verilog-A implementation/validation (see below). This is a "hot" R&D topic in our domain. I would suggest to invite the researchers working on the FOSS TCAD/EDA tools for compact modeling support. There is interesting work done by GnuCap, ngspspice, Qucs, Xyce teams and many others. Let's also explore that topics with your local partners eg: Cogenda and local host in Guangzhou 

I will be gald if you can introduce myself to your organization team in Guangzhou, too.

-- thanks and have a nice weekend -- wladek;

 

 Many thanks.

regards,

min

On Wed, Mar 2, 2022 at 4:53 PM Wladek Grabinski <wladek@grabinski.ch> wrote:

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

Q1 2022 MOS-AK Panel

Online Publications

The Extended MOS-AK Committee, has organized a very first MOS-AK Panel to discuss the FOSS EDA tools for the compact/SPICE modeling and its Verilog-A standardization and implementation. The Q1 2022 MOS-AK Panel was organized as the virtual/online event on Feb.25, 2022, with practive participation of leading FOSS EDA developers representing GnuCap, ngspice, Qucs, Xyce teams.

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see submitted slide presentations online at corresponding link:

https://www.mos-ak.org/panel_Q1_2022/

The MOS-AK Panelists have also contributed to FOSS EDA/Verilog-A SWOT Analysis, with selected points listed in the table below. The FOSS EDA community has a number of challenges to address, in particular, securing financial support for FOSS EDA tools developments, especially for those outside of the corporate/academic environment, is of primary concern.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru the Next 2022 Year, including:

• Spring MOS-AK Workshop (online) Mar/Apr 2020
• 4th MOS-AK/LAEDC Workshop, Cancun (MX) July 2022
  
• 6th Sino MOS-AK Workshop (CN), Aug. 2022
• 20th MOS-AK/ESSDERC/ESSCIRC, Milano Sept.19, 2022
• 3rd MOS-AK/India Conference, Hyderabad (IN) Postponed 2022
• 15th US MOS-AK Workshop, Silicon Valley (US) Dec. 2022
• in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski on the behalf of International MOS-AK Committee

WG02032022

Table: FOSS EDA/Verilog-A SWOT Analysis

Strengths	Weaknesses
High number of potential users both in terms of EDA companies/vendors and designers High number of potential contributors once a tool as been established as "gold standard"	At least a bit financial support will be needed in the long-run
Opportunities	Challenges
A "gold standard" Verilog-A compiler, i.e. sth. Like gcc, g++ or gfortran is currently not available for Verilog-A Improve the usefulness of open-source tools dramatically Enabler for research around the world  Further improving the Verilog-A standard and enabling new modeling technologies in the long-term	Securing financial support for FOSS developments, especially for those outside of the corporate/academic environment Teamwork, between projects

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[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).

[paper] Progress in Organic Photodiodes through Physical Process Insights

Hrisheekesh Thachoth Chandran,Cenqi Yan,Gang Li

Progress in Organic Photodiodes through Physical Process Insights

Adv. Energy Sustainability Res. (2022) 2200002.

DOI: 10.1002/aesr.202200002

   

*The Hong Kong Polytechnic University

Abstract: Photodetectors based on organic materials have enormous potential due to their attractive optoelectronic and mechanical properties. In recent years, some of the performance metrics comparable to the conventional inorganic photodetectors have been realized in visible-range organic photodiodes (OPDs). These advancements in OPDs are mainly driven by innovations in device engineering and material design. However, insights into the fundamental performance limiting factors are imperative to further understand, optimize, and predict the performance metrics of OPD devices beyond conventional wisdom. In this review, the major progress in understandings related to trap state, charge transfer state, and noise/detectivity limits in OPD devices are highlighted.

FIG: (a) Simplified device architecture of cavity-enhanced photodiode. (b) Simplified energy-level diagram with the demonstration of photon absorption, charge generation, and charge transport processes. 

Acknowledgements: This work was supported by the following grants: Research Grants Council of Hong Kong (GRF grant 15221320, CRF C5037-18G), National Science Foundation of China (NSFC 51961165102), Shenzhen Science and Technology Innovation Commission (Project No. JCYJ 20200109105003940), and the Hong Kong Polytechnic University (The Sir Sze-yuen Chung Endowed Professorship Fund (8-8480) and Postdoc Matching Fund scheme (1-W15V)).

[Open-Source FPGA Foundation] 4-day hands-on workshop

[Open-Source FPGA Foundation] is pleased to bring a 4-day hands-on workshop hosted by GS Micro Electronics on #opensource #integratedcircuits #designtools View details and register using the link https://t.co/GM6zTuOw3Q #semi https://t.co/2Lit4lvrfs

— Wladek Grabinski (@wladek60) Mar 2, 2022

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