[mos-ak] [2nd Announcement] 17th International MOS-AK Workshop Silicon Valley, December 11, 2024

17th International MOS-AK Workshop 

Silicon Valley, December 11, 2024

   

2nd Announcement and C4P

The 17th International MOS-AK Workshop on Compact/SPICE Modeling will take place on Dec.11, 2024, in the timeframe of IEDM and Q4 CMC Meetings. This event is coorganized by Keysight Technologies, our local online host and partner, and the Extended MOS-AK TPC Committee. We cordially invite you to participate in the upcoming MOS-AK workshop, where you will have the opportunity to learn from leading experts in the field of the SPICE and Verilog-A modeling, OpenPDKs, and FOSS CAD/EDA IC designs. This event promises to be an invaluable experience for professionals and enthusiasts alike, offering deep insights and practical knowledge in these critical areas of the electron devices modeling and electronic design automation.

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Device level modeling for Agroelectronics, Bio/Med, IoT applications
• Device cryogenic operation for Quantum Computing 
  
• Nanoscale semiconductor devices/circuits and its reliability/ageing
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies, Open Access PDK
  (eg: Skywater 130nm CMOS, GF 180nm, IHP 130nm RF BiCMOS, OpenSUSI) '

Online Abstract Submission is open 

(any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open 

(any related enquiries can be sent to registration@mos-ak.org)

Important Dates:

• 2nd Announcement: Nov. 2024
• Final Workshop Program: Dec. 2024
• MOS-AK Workshop: Dec.11, 2024
• in timeframe of Q4 CMC and IEDM Meetings

W.Grabinski for Extended MOS-AK Committee

WG021224

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1st Semiconductor Design Workshop in Yamagata

Ministry of Economy, Trade and Industry

Tohoku Bureau of Economy, Trade and Industry

1st Semiconductor Design Workshop in Yamagata

Date: December 20, 2024 (Friday)

Time: 1:00pm-5:00pm

Why not experience semiconductor design hands-on with the instructor on your own PC? This is a valuable opportunity to learn the basics of semiconductor design with intimate and detailed guidance in a small class setting.

[paper] Roadmap for Schottky Barrier Transistors

Eva Bestelink1*, Giulio Galderisi2, Patryk Golec1, Yi Han3, Benjamin Iniguez4, Alexander Kloes5, Joachim Knoch6, Hiroyuki Matsui7, Thomas Mikolajick2,8, Kham M. Niang9, Benjamin Richstein6, Mike Schwarz5, Masiar Sistani10, Radu A. Sporea1, Jens Trommer2, Walter M. Weber10,
Qing-Tai Zhao3 and Laurie E. Calvet11

Roadmap for Schottky Barrier Transistors

IOP Nano Futures in press (2024)

DOI: 10.1088/2399-1984/ad92d1

1 Advanced Technology Institute, University of Surrey, Guildford, UK
2 Namlab gGmbH, Nöthnitzer Str. 64a, 01187 Dresden, Germany
3 Peter Grünberg Institute, Forschungszentrum Jülich, 52428 Jülich, Germany
4 DEEEA, Universitat Rovira I Virgili, Tarragona, Spain,
5 NanoP, THM University of Applied Sciences, 35390 Giessen, Germany,
6 Institute of Semiconductor Electronics, RWTH Aachen University, Germany
7 Research Center for Organic Electronics (ROEL), Yamagata University, Japan
8 Chair for Nanoelectronics, TU Dresden, Germany
9 Electrical Engineering, Cambridge University, UK
10 Institute of Solid State Electronics, TU Wien, Vienna, Austria
11 LPICM, CNRS-Ecole Polytechnique, IPP, 91120 Palaiseau, France

Abstract: In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier, as an asset for device functionality. We discuss source gated transistors, which allow for excellent electronic characteristics for low power, low frequency environmentally friendly circuits. Also considered are reconfigurable field effect transistors, where the presence of two or more independent gate electrodes can be used to program different functionalities at the device level, providing an important option for ultrasecure embedded devices. Both types of transistors can be used for neuromorphic systems, notably by combining them with ferroelectric Schottky barrier transistors, which enable a large number of analog states. At cryogenic temperatures, SB transistors can advantageously serve for the control electronics in quantum computing devices. If the source/drain of the metallic contact becomes superconducting, Josephson junctions with a tunable phase can be realized for scalable quantum computing applications. Developing applications using Schottky barrier devices requires physicsbased and compact models that can be used for circuit simulations, which are also discussed. The roadmap reveals that the main challenges for these technologies are improving processing, access to industrial technologies and modeling tools for circuit simulations.

Fig: Illustration of the different applications of the SB Devices

Aknowleegements: RAS and EB acknowledge support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/V002759/1, EP/R028559/1, and EP/R511791/1, and from the Royal Society of Great Britain under Grants IES\R2\202056, IES\R3\193072, IEC\R3\183042, and IES\R3\170059. JT and GG are supported from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101135316, SENSOTERIC. LEC and BI are supported from the European Union’s Horizon Europe research and innovation program under grant agreement No 101099555, BAYFLEX. Q-T Zhao, Y. Han, B. Richstein and J. Knoch gratefully acknowledge support from Deutsche Forschungsgemeinschaft under grant nos. KN 545/28, KN 545/29, and ZH-639/3. Q-T Zhao acknowledges partially support by the German BMBF project “NeuroTEC” (16ME0398K). KMN acknowledges support from the Engineering and Physical Sciences Research Council (EPSRC) under Grants EP/M013650/1 and EP/W009757/1. LEC acknowledges funding from the ANR under contract ANR-21-FAI1-0006-01.

[paper] Bendable non-silicon RISC-V microprocessor

Emre Ozer, Jedrzej Kufel, Shvetank Prakash2, Alireza Raisiardali, Olof Kindgren3, Ronald Wong,
Nelson Ng, Damien Jausseran, Feras Alkhalil, David Kong2, Gage Hills2, Richard Price
and Vijay Janapa Reddi2

Bendable non-silicon RISC-V microprocessor

Nature, vol. 634, pp. 341–346 (2024) 

DOI: 10.1038/s41586-024-07976-y

1 Pragmatic Semiconductor, Cambridge, UK
2 Harvard University, Cambridge, MA, USA

3 Qamcom, Karlstad, Sweden

Abstract: Semiconductors have already had a very profound effect on society, accelerating scientific research and driving greater connectivity. Future semiconductor hardware will open up new possibilities in quantum computing, artificial intelligence and edge computing, for applications such as cybersecurity and personalized healthcare. By nature of its ethos, open hardware provides opportunities for even greater collaboration and innovations across education, academic research and industry. Here we present Flex-RV, a 32-bit microprocessor based on an open RISC-V instruction set fabricated with indium gallium zinc oxide thin-film transistors on a flexible polyimide substrate, enabling an ultralow-cost bendable microprocessor. Flex-RV also integrates a programmable machine learning (ML) hardware accelerator inside the microprocessor and demonstrates new instructions to extend the RISC-V instruction set to run ML workloads. It is implemented, fabricated and demonstrated to operate at 60kHz consuming less than 6mW power. Its functionality when assembled onto a flexible printed circuit board is validated while executing programs under flat and tight bending conditions, achieving no worse than 4.3% performance variation on average. Flex-RV pioneers an era of sub-dollar open standard non-silicon 32-bit microprocessors and will democratize access to computing and unlock emerging applications in wearables, healthcare devices and smart packaging.

FIG a. Layout of the 9×6 mm2 test chip containing two Flex-RV microprocessors

b. The FlexPCB on which the die is assembled.

Data availability
Source data are provided with this paper.

Code availability

Serv is an open-source CPU, which is freely available at GitHub (https://github.com/olofk/serv). The source code of the test benchmarks, the changes made in the Serv CPU Verilog code, and the Verilog code of the ML hardware accelerator are available from the corresponding author upon request.

[WOSET] Q&A at OpenPDK session

Indira Iyer Almeida, Sumanto Kar, Wladek Grabinski joined a great Q&A at #OpenPDK session at #WOSET

Workshop on Open-Source EDA Technology (WOSET) was organized by Prof. Matthew Guthaus and his R&D Team. WOSET 2024 Schedule is available online