SIA/Oxford Economics Report: Robust federal incentives for domestic chip manufacturing

SIA/Oxford Economics Report:
Robust federal incentives for domestic chip manufacturing would create an average of nearly 200,000 American jobs annually as fabs are built and add nearly $25 billion annually to U.S. economyhttps://t.co/Ahvt2ozLO8#semi pic.twitter.com/DeJ7cdJu98

— Wladek Grabinski (@wladek60) May 21, 2021

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from Twitter https://twitter.com/wladek60

May 21, 2021 at 11:03AM
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DIY chip for $10k Efabless, a community chip creation platform

DIY chip for $10k
Efabless, a community chip creation platform, today announced the launch of its new chipIgnite program to bring #chip #design and #fabrication to the masses.https://t.co/rmaDoHNaJZ #semi pic.twitter.com/VnbxVThEf2

— Wladek Grabinski (@wladek60) May 21, 2021

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from Twitter https://twitter.com/wladek60

May 21, 2021 at 09:59AM
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[Program] SICT2021 aims to bridge the gap between research in the Information and Communications Technology (ICT) and the overarching and inter-related social, environmental, and economic questions of our time https://t.co/fyMzfIun8Z #semi https://t.co/gtU7xulUHt

[Program] SICT2021 aims to bridge the gap between research in the Information and Communications Technology (ICT) and the overarching and inter-related social, environmental, and economic questions of our time https://t.co/fyMzfIun8Z #semi pic.twitter.com/gtU7xulUHt

— Wladek Grabinski (@wladek60) May 21, 2021

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from Twitter https://twitter.com/wladek60

May 21, 2021 at 09:52AM
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#TSMC trumps #IBM’s “#2nm” chip tech hyperbole with “#1nm” claim https://t.co/xWTVO8ygW6 #semi https://t.co/EUetFKHidw

#TSMC trumps #IBM’s “#2nm” chip tech hyperbole with “#1nm” claimhttps://t.co/xWTVO8ygW6#semi pic.twitter.com/EUetFKHidw

— Wladek Grabinski (@wladek60) May 19, 2021

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from Twitter https://twitter.com/wladek60

May 19, 2021 at 02:54PM
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[paper] An Accurate Analytical Modeling of Contact Resistances in MOSFETs

G. Bokitko, D. S. Malich, V. O. Turin*, and G. I. Zebrev

An Accurate Analytical Modeling of Contact Resistances in MOSFETs

Preprint · May 7, 2021 DOI: 10.13140/RG.2.2.29348.40321

National Research Nuclear University MEPHI, Moscow, Russia;
*Orel State University, Russia;

Abstract: As the MOSFET channel lengths decrease, the influence of parasitic source-drain resistance on the current characteristics becomes more and more important. The contact resistance is becoming a growing impediment to transistor power and performance scaling. This is a common challenge for SOI FETs, FinFETs and GAAFETs and any other type of transistor. Most of the modern compact models that are used in circuits simulations are too much technology oriented. We find it important to construct an analytical approach that could be served as a basis for compact modeling. This approach is based on analytical solution Kirchhoff’s equations and on the diffusion-drift field effect transistor model.

Fig: Equivalent MOSFET circuit with series resistance