Apr 19, 2017

2017 National Academy of Inventors Fellow Induction

National Academy of Inventors Fellow Induction
Chenming Hu
TSMC Distinguished Professor Emeritus at UC Berkeley


Among all NAI Fellows there are now 94 presidents and senior leaders of research universities and non-profit research institutes, 382 members of the National Academies of Sciences, Engineering, and Medicine, 31 inductees of the National Inventors Hall of Fame, 45 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science, 28 Nobel Laureates, 216 AAAS Fellows, 126 IEEE Fellows, and 116 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions. [read more...]

Apr 18, 2017

2017 IEEE Andrew S. Grove Award

Prof. Sorin Cristoloveanu,  CNRS at IMEP-LAHC
2017 IEEE Andrew S. Grove Award Recipient
“For contributions to silicon-on-insulator technology and thin body devices”

A visionary device physics researcher, Sorin Cristoloveanu saw the potential that silicon-on-insulator (SOI) technology held for the semiconductor industry in producing competitive microelectronics components with improved performance when others considered it a niche field. As early as 1976, he discovered key mechanisms of thin-body devices that have led to the development of transistors from the simplest (zero gate) to the most complicated (four gates). Among several concepts unveiled by his group, the demonstration during the 1980s that volume inversion occurs in all nano-body devices was revolutionary at the time and helped drive research that led to double-gate transistors and today’s tri-gate FinFET devices. His Pseudo-MOSFET method developed in 1992 has become an industry standard for wafer monitoring without having to actually fabricate devices. More recently, Cristoloveanu’s SOI expertise has led to innovative devices for low-power memory and sharp-switching circuits. An IEEE Fellow, Cristoloveanu is the director of research at CNRS at IMEP-LAHC, Grenoble, France [read more...]

Apr 17, 2017

[paper] Artificial neural network design for compact modeling of generic transistors

Artificial neural network design for compact modeling of generic transistors
(J Comput Electron; pp. 1-8;  2017)
Lining Zhang and Mansun Chan
Department of ECE, Hong Kong University of Science and
Technology, Kowloon, Hong Kong

Abstract: A methodology to develop artificial neural network (ANN) models to quickly incorporate the characteristics of emerging devices for circuit simulation is described in this work. To improve the model accuracy, a current and voltage data preprocessing scheme is proposed to derive a minimum dataset to train the ANN model with sufficient accuracy. To select a proper network size, four guidelines are developed from the principles of two-layer network. With that, a reference ANN size is proposed as a generic three-terminal transistor model. The ANN model formulated using the proposed approach has been verified by physical device data. Both the device and circuit-level tests show that the ANN model can reproduce and predict various device and circuits with high accuracy [read more...]

(Published online April 9, 2017 http://dx.doi.org/10.1007/s10825-017-0984-9)

Apr 4, 2017

Starting Framework of the IRDS Roadmap

IEEE has announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS), an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS [read more...]

The series of white papers delivers the starting framework of the IRDS roadmap - and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:
The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC) scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies [read more...]

Mar 24, 2017

NIST Digital Library of Mathematical Functions