Édney M. V. Freitas, Nicolas Guimarães, Rafael Maria, Felipe Costa,
Guilherme Milani, Bruno Sanchesand, Wilhelmus Van Noije
Using Open Source EDA Tools in ASICs for HEP: A Mixed Comparison
arXiv:2512.06122v1 [hep-ex] 5 Dec 2025
1. Escola Politécnica da Universidade de São Paulo, Brazil
Abstract: This work compares open-source electronic design automation tools with a commercial environment using three representative integrated circuit blocks in the IHP 130nm open PDK: a common-mode noise filter, a finite-state machine, and a voltage-controlled oscillator. The study reports design effort and quality of results for digital logic, including area, power, and timing closure, and examines analog layout feasibility. For the finite-state machine at 50 MHz, the open-source flow reached 0.029 mm2 (post-layout) and 4.37 mW (estimated) with 828 standard cells, whereas the commercial flow achieved 0.019 mm2 and 2.00 mW with 497 cells, corresponding to increases of 53% in area and 118% in power. The common-mode noise filter totals 1.879 mm2 with 1703 flipflops at 50 MHz. The voltage-controlled oscillator occupies 0.0025 mm2 and achieves a simulated maximum oscillation frequency of 2.65 GHz. The contribution is a side-by-side quantification of quality of results across digital and analog blocks in the IHP open PDK. The results indicate that open-source tools are viable for early prototyping, training, and collaboration, while commercial flows retain advantages in automation and quality of results when strict targets on power and area or precision analog layout are required.
FIG: Digital layouts under identical constraints. Layer colors are tool specific.
Acknowledgments: This work was financed, in part, by the São Paulo Research Foundation (FAPESP), Brazil, Grants #2024/04802-9 and #2024/06703-8, by CNPQ Grant #134869/2024-9. This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES), Brazil - Finance Code 001.
