[paper] GaN-on-Si HEMT

Rijo Baby^a, Manish Mandal^b, Shamibrota K. Roy^b, Abheek Bardhan^a, Rangarajan Muralidharan^a, Kaushik Basu^b, Srinivasan Raghavan^a, Digbijoy N. Nath^a

8A, 200V normally-off cascode GaN-on-Si HEMT: From epitaxy to double pulse testing

Microelectronic Engineering, Volume 282, 2023, 112085,

DOI: 10.1016/j.mee.2023.112085.

a Center for Nanoscience and Engineering (CeNSE), (IISc Bangalore (IN)
b Department of Electrical Engineering, IISc Bangalore (IN)

Abstract: In this paper, we provide a comprehensive study on all aspects of development of normally-off multi-finger III-nitride HEMT on Silicon in cascode configuration. AlGaN/GaN HEMT epi-stack with in situ SiN cap was grown on 2" Silicon (111) using MOCVD, utilizing a 2-step AlN nucleation, step-graded AlGaN transition layer and C-doped GaN buffer. Depletion-mode HEMTs in winding gate geometry with a gate width of 30mm were fabricated with thick electroplated metal contacts and an optimized bilayer SiN passivation. Devices were diced and packaged in TO254 with conducting epoxy and Au-coated ceramic substrate. These packaged D-mode HEMTs exhibited a threshold voltage (Vth) of −12V, maximum ON current of 10A and a 3-terminal hard breakdown in excess of 400V. Bare dies of D-mode HEMTs were then integrated with commercially procured silicon MOSFET in a TO254 package in cascode configuration to achieve Vth>2V, ON current of 8Aand breakdown >200V. The normally-off cascaded GaN HEMTs were subjected to various gate and drain stress measurements and were found to exhibit a Vth shift of 10 mV after 1000 s of positive gate (+5V) stress. The input and output capacitances of the cascode devices were measured to be 1 nF and 0.8 nF, respectively. The 3rd quadrant operation was checked at 8 A on-state current level to reveal a lower voltage drop of 0. V. Finally, cascode HEMTs were subjected to double pulsed testing (DPT) using a half-bridge evaluation board. On and off rise times of 52 ns and 59 ns were obtained along with energy loss of 25 μJ and 20 μJ, respectively, for devices switched at 8A,100V.

FIG: 8A, 200 V normally-off cascode GaN-on-Si HEMT

Acknowledgement: This research was supported by ISRO/SCL. We also acknowledge funding support from MHRD through the NIEIN project, from MeitY and DST Nano Mission through NNetRA. We thank the Micro and Nano Characterization Facility (MNCF) staff and facility technologists of the National Nano Fabrication Facility (NNFC). We thank Anirudh Venugopalarao, Parimalazhagan Serralan, Mr. Veera Pandi N, Dr. M.M Nayak, Mr. Malingu G and Bharath Kumar M for their support.