[paper] Hot Carrier Degradation in n-MOSFETs

S. Mahapatra and U. Sharma, 

Department of Electrical Engineering,

IIT Bombay, Mumbai 400076, India

A Review of Hot Carrier Degradation in n-Channel MOSFETs

Part I: Physical Mechanism

IEEE TED, vol. 67, no. 7, pp. 2660-2671, July 2020

DOI: 10.1109/TED.2020.2994302

Abstract: Transistor parametric drift due to conduction mode hot carrier degradation (HCD) in n-MOSFETs is reviewed, for long- and short-channel length (LCH) devices having different source/drain (S/D) junction structures. The HCD magnitude and time kinetics shape are discussed for stress under different gate (VG) and drain (VD) biases with varying VG/VD ratio, and without and with substrate bias (VB). Post-dc stress kinetics is discussed. The published data are qualitatively analyzed to identify the roles of different underlying physical mechanisms. In part II of this article, impacts of technology scaling and stress temperature (T) and comparison of dc and ac stress are discussed.

Fig: (a) Schematic of an LDD MOSFET. Carrier heating process, primary and secondary impact ionization, respectively, at VB=0V and VB < 0V, and gate injection are shown. Charges due to HCD in the channel (square), gate–drain overlap (triangle), and spacer (diamond) regions are shown. (b) Energy band diagram showing the energy thresholds for impact ionization, and electron and hole injection over their respective channel-oxide barriers. AHI process is illustrated at (VG–VD) > 0V.