[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin

Distinguishing capture cross section parameter between 

in GIDL erase compact model and TCAD

Japanese Journal of Applied Physics. 2021 Oct 14.

 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.

[https://t.co/pmnr27KGAy] #Alibaba Announces #opensource #RISC-V-Based Xuantie Series #Processors #semi #chips #riscv https://t.co/VTIRXyYpEI

[https://t.co/pmnr27KGAy] #Alibaba Announces #opensource #RISC-V-Based Xuantie Series #Processors #semi #chips #riscv https://t.co/VTIRXyYpEI

— Wladek Grabinski (@wladek60) Oct 20, 2021

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October 20, 2021 at 01:36PM
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Apple Unveils New M1 Pro, Monster M1 Max SoCs

[https://t.co/rrssJ7q5A5] Apple Unveils New M1 Pro, Monster M1 Max SoCs #semiconductor #intel #apple #customsilicon #competition #leadership #semi https://t.co/9wsFqWvLXN

— Wladek Grabinski (@wladek60) Oct 19, 2021

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President Macron wants #EU to double its #semi #production

Like Thierry Breton, the president Emmanuel Macron wants #EU to double its#semi  #production capacity. The #France and #Europe want to invest €6 billion and €40 billion respectively. [ @VIPress, #semiconductors, #chips] https://t.co/AzzG721WX9

— Wladek Grabinski (@wladek60) Oct 13, 2021

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[paper] Parameter Extraction of Power MOSFET Models

Michihiro Shintani, Aoi Ueda and Takashi Sato

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation

IEEE Transactions on Power Electronics (2021)

DOI:  10.1109/TPEL.2021.3118057

 
Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma (J)

Graduate School of Informatics, Kyoto University (J)
 

Abstract: The extraction of the model parameters is as im- portant as the development of compact model itself because simulation accuracy is fully determined by the accuracy of the pa- rameters used. This study proposes an efficient model-parameter extraction method for compact models of power MOSFETs. The proposed method employs automatic differentiation (AD), which is extensively used for training artificial neural networks. In the proposed AD-based parameter extraction, gradient of all the model parameters is analytically calculated by forming a graph that facilitates the backward propagation of errors. Based on the calculated gradient, computationally intensive numerical differentiation is eliminated and the model parameters are efficiently optimized. Experiments are conducted to fit current and capacitance characteristics of commercially available silicon carbide MOSFET using power MOSFET models having 13 model parameters. Results demonstrated that the proposed method could successfully derive the model parameters 3.50× faster than a conventional numerical-differentiation method while achieving the equal accuracy.

Fig: Backward propagation mode. The dashed arrows indicate the path from E to SCALE.

The propagated values on the path in the backward propagation are highlighted

Acknowledgment: This work was partially supported by JST-OPERA Program Grant Number JPMJOP1841, Japan. The part of this work is also supported by JSPS KAKENHI Grant 20H04156 and 20K21793.