#MEMS becoming more #human

#MEMS becoming more #human https://t.co/aPG0GWl0Yq #semi https://t.co/kkUyTs4HN7

— Wladek Grabinski (@wladek60) Jul 21, 2021

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from Twitter https://twitter.com/wladek60

July 21, 2021 at 10:22AM
via IFTTT

VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST

 

This 60-min webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to Verilog language and is a part of a mixed-signal SoC

If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred

This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification

Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.

Agenda:

1. "FPGA on eSim"
   Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2. "chipIgnite Program"
   Guest Speaker - Mike Wishart, CEO eFabless
3. "Tapeout World Program"
   Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4. "Mixed-signal RISC-V based SoC on FPGA"
   Webinar Instructor - Shivani Shah

Webinar Curriculum:
1) Introduction
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
12) Conclusion

Register here (if you don't see the form, please refresh page):
https://lnkd.in/gByg6fZ

[Announcement] ToM 2021/2 online on September 21st-23rd

ToM2021/2 course will be held online on September 21st-23rd, 2021 with the following program:

September 21 2021
    14:00 – 17:30 Jussi Jansson (Oulu University, Finland) - "Time-to-digital converters and related applications"
September 22 2021
    09:00 – 12:30 Luca Scandola (Infineon Technologies, Italy), "Introduction to DC-DC conversion suitable for automotive application: from the theory to the modelization with practical examples"
    14:00 – 17:30 Benoit Bakeroot (Ghent University, Belgium), "GaN semiconductor devices for power electronics: overview, status and future perspectives"
September 23 2021
    09.00 – 12:30 Qiang Li (UETSC, China), "Subthreshold and near-threshold ADC techniques"
    14:00 – 17:30 Andrea Mazzanti (University of Pavia, Italy) and Enrico Monaco (Inphi, Italy), "Introduction and advances in serial links"

=============================================

Registration is mandatory to attend the course:
http://www.innotechevents.com/index.php?page=ToM/RegistrationForm.html

Registered participants will receive:
- on-line attendance to all lectures
- pdf material for all lectures
- certificate of participation
- final exam with certificate (if needed)

We look forward to virtually meeting you !!!!

More information at:
http://www.innotechevents.com/index.php?page=ToM/ToM.html

Best regards
Andrea Baschirotto

#SiFive Technical Symposium // India and Bangladesh

#SiFive Technical Symposium // India and Bangladesh https://t.co/ssXogdcGYQ #RISC-V #semi #core #IP https://t.co/t1Ti0wrNnp

— Wladek Grabinski (@wladek60) Jul 15, 2021

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from Twitter https://twitter.com/wladek60

July 15, 2021 at 11:41AM
via IFTTT

Last chance for IEEE Mauritius Conference

Dear colleagues, Due to many requests, the paper submission deadline has been extended to 25th July 2021 ! This is last due date . We are pleased to invite you to participate to the IEEE - International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME) which will be held in Mauritius, the Paradise Island on 07-08 October, 2021. The ICECCME is the premier event that brings together industry professionals, academics, and engineers from the related institutions to exchange information and ideas on electrical, computer, communications and mechatronic engineering. All accepted and presented papers will be submitted to IEEE Xplore for publication. The extended versions of selected papers will be published in SCI-indexed Energies journal with IF: 2.702 Due to the Covid pandemic, ICECCME will be held both face-to-face and online. Participants can make their presentations online. You can see all the details on the conference web page: http://www.iceccme.com The conference will take place in Mauritius surrounded by the warm Indian Ocean. Mauritius is one of the best holiday destinations in the world with clear warm sea waters, attractive beaches, tropical fauna and flora. Come to Mauritius, reward yourself! If you would like to be a reviewer... You can review the papers from our conferences and journal. By acting as a reviewer, you can earn discounts on conference participation fees (from any of our conferences). In addition we will send reviewer certificate. Click here to reviewer application Important Dates: Paper Due :  25 July, 2021 Acceptance Notification :  10 August, 2021 Early Registration Deadline: 15 August, 2021 Camera Ready Due : 20 August, 2021 Conference Dates: 7-8 October 2021 Best regards, Conference Organizing Team E-mail: info@iceccme.com   Phone(Whatsapp): +90 532 6425237 Projenia R&D Co. Erciyes TGB, No:67/10 TR Follow us on social media to be informed for our events.   If you do not want to receive mail from us anymore, please unsubscribe.  When you unsubscribe from the list, definetely no e-mail will be sent to you after that.