5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh

5 #benefits of contributing to #opensource projects https://t.co/qKsBgkR9Uh

— Wladek Grabinski (@wladek60) October 12, 2017

from Twitter https://twitter.com/wladek60

October 12, 2017 at 09:30AM
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Intern/Student in SW Eng. for Power Management f/m

Job Description: You will be responsible for developing a SW tool enabling an user friendly and efficient framework to program system-on-chip. The flexibility of our power management solution thanks to enhanced customization is indeed a critical asset requiring a reliable tool from programming definition to release. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams [read more...]

Your main tasks in this full time position min 5 months up to 12 months will be to:

• Create several functions/add-ons enhancing entry interface
• Develop a compiler to better explore new chip architectures-Integrate compiler output with existing tools
• Implement sanity checkers detecting
• Develop test scenarios and requirements for chip validation
• Contribute to the reporting and documentation for other teams and management

[read more...]

#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE

#Linux Now Has its First #OpenSource #RISC-V Processor https://t.co/cdM2NNXBoE

— Wladek Grabinski (@wladek60) October 7, 2017

from Twitter https://twitter.com/wladek60

October 07, 2017 at 11:33PM
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#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 https://t.co/91YMe1jKV1

#Apple #Opensource-d the #iOS Kernel for #ARM CPUs https://t.co/LUUYUnRSm2 http://pic.twitter.com/91YMe1jKV1

— Wladek Grabinski (@wladek60) October 5, 2017

from Twitter https://twitter.com/wladek60

October 05, 2017 at 12:06PM
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[paper] A Novel Reconfigurable sub-0.25V Digital Logic Family Using the Electron-Hole Bilayer TFET

Cem Alper, Jose Luis Padilla, Pierpaolo Palestri, Senior Member, IEEE

and Adrian M. Ionescu, Fellow, IEEE

IEEE Journal of the Electron Devices Society

doi: 10.1109/JEDS.2017.2758018

Abstract: We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (”n-gate” and ”p-gate”) of the electron-hole bilayer TFET (EHBTFET). If the device is designed to conduct only under certain conditions e.g. when Vn-gate = VDD and Vp-gate = 0, it then shows an ’XOR-like’ behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections [read more...]

FIG: Sketch of the hetero-gate InGaAs EHBTFET and its circuit symbol.