The Ten Commandments for Effective Standards

The Ten Commandments for Effective Standards:

Practical Insights for Creating Technical Standards

Karen Bartleson (Author)

Publisher: Synopsys Press (May 7, 2010)
Language: English
ISBN-10: 1617300020
ISBN-13: 978-1617300028

About the Author:
Karen Bartleson has three decades' experience in the computer chip industry. She is known for her work in the area of standards for electronic design automation, and is also one of the pioneers into social media in her industry, including Twitter. She is the author of "The Standards Game," a blog focused on the standards arena. Karen holds a BSEE from California Polytechnic State University, San Luis Obispo, California, and was the recipient of the Marie R. Pistilli Women in Design Automation Achievement Award in 2002. Her Twitter handle is @karenbartleson. --This text refers to the Paperback edition.

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

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MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
   * Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
   * Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
   * Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
   * Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
   * David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
   * Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
   * Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
   * Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

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[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

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You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
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For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.

SPICE update from Mentor

Daniel Payne talked with See-Mei Chan, Technical Marketing Manager at Mentor Friday morning because they couldn’t connect in Anaheim earlier this week. Daniel wanted to better understand what is new with Eldo, the SPICE circuit simulator at Mentor.

Read more in June 18th, 2010 post by Daniel Payne in Analog Fast SPICE, DAC 2010, Fast SPICE, SPICE circuit simulation.

News and Views: Nature Nanotechnology

A. M. Ionescu

Electronic devices: Nanowire transistors made easy

Nature Nanotechnology, vol. 5, iss. 3, pp. 178 – 179, March 2010

Figure (a) A junction FET is turned on in the (strong) inversion condition, when a channel of minority carriers is formed just under the gate, and junction barriers to their flow are reduced. The off state of the junction FET corresponds to high junction barriers and the suppression of the inversion channel. The horizontal red line shows the bottom of the depletion region, and the slanted red lines indicate the limits of the depletion region controlled by the gate. (b) In contrast, the on state of a junctionless FET is obtained in 'flat band' conditions, with majority carriers travelling through a highly doped film. The device (which requires a thin-film silicon-on-insulator substrate) turns off when the gate-controlled depletion extends over the whole film. Both devices operate with the source grounded and a positive potential applied to the drain. Vt denotes the threshold voltage (positive for the n-type devices). Similar descriptions apply to the operation of complementary p-type FETs. Blue and red colours depict electron and hole doping respectively, with a darker colour indicating heavier doping. The white regions correspond to the depletion regions, and the green colour represents the gate oxide.

References

1. Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925)
2. Shan, Y., Ashok, S. & Fonash, S. J. Appl. Phys. Lett. 91, 093518 (2007)
3. Lin, Y.-W., Marek-Sadowska, M., Maly, W., Pfitzner, A. & Kasprowicz, D. in Int. Conf. Computer Design 557–562 (IEEE, 2008)
4. Soree, B. & Magnus, W. in 10th Int. Conf. Ultimate Integration of Silicon 245–248 (IEEE, 2009)
5. Lee, C. W. et al. Appl. Phys. Lett. 94, 053511 (2009)
6. Colinge, J. P. et al. Nature Nanotech. 5, 225–229 (2010)
7. Tsutsui, K. et al. in Int. Workshop Nano CMOS 56–68 (IEEE, 2006)
8. Aoyama, T. et al. in Int. Workshop Junction Technol. 110–115 (IEEE, 2009)