[paper] Ultra-High Voltage SiC IGBT

Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance

Using Calibrated TCAD Model

Daniel Johannesson^1,2, Keijo Jacobs¹, Staffan Norrga¹, Anders Hallén³, 

Muhammad Nawaz² and Hans-Peter Nee^1,2

Materials Science Forum Submitted: 2019-09-19

ISSN: 1662-9752, Vol. 1004, pp 911-916  

DOI:10.4028/www.scientific.net/MSF.1004.911

¹Division of Electric Power and Energy Systems, KTH , Sweden
²ABB Corporate Research, Västerås, Sweden
³Division of Electronics, KTH, Sweden

Abstract: In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general highpower application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

Fig: 4H-SiC IGBT structure implemented in 2D TCAD simulator

Acknowledgment This work was funded through SweGRIDS, by the Swedish Energy Agency and ABB.

[paper] Multi-Bridge-Channel Field Effect Transistor

Leakage Performance Improvement in Multi-Bridge-Channel Field Effect Transistor

(MBCFET) by Adding Core Insulator Layer 

Saehoon Joung^1,2, Student Member, IEEE and SoYoung Kim², Senior Member, IEEE 

SISPAD 2019 

DOI:10.1109/sispad.2019.8870498 

¹Samsung Electronics Co. Foundry Division, Yield Enhancement, Process Integration Engineering Group, Ltd Kiheung, Republic of Korea
²College of Information and Communication Engineering,Sungkyunkwan University, Suwon,Gyeounggi-do, Republic of Korea

Abstract: Altering from existing planar devices to FinFETs has revolutionized device performance, but demands of leakage and gate controllability are increasing relentlessly. Gate all around field effect transistor (GAAFET) is expected to be the next-generation device that meets these needs. This paper suggests a way to improve the gate electrostatic characteristics by adding an oxidation process to the conventional multi-bridgechannel field effect transistor (MBCFET) process. The main advantage of the proposed method is that a device with ultimate electrostatic properties can be implemented without changing the complex and expensive photo-patterning. In the proposed device, the immunity of short channel effects is enhanced in a single transistor. And the performance of ring oscillator (RO) and SRAM was confirmed to be improved by TCAD mixed-mode simulation.

FIG: MBCFET Process Flow Comparison 

 

Acknowledgement: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. NRF-2017R1A2B2003240). The TCAD tools were supported by the IC Design Education Center (IDEC).

[mos-ak] Fwd: MOS-AK / IEEE-EDS-MQ / SSB-MOS Workshops at THM - Deadline extended

Dear colleagues and friends, 

please note that the registration deadline for the

Joint Spring MOS-AK Workshop and 

Symposium on Schottky Barrier MOS (SB-MOS) devices with 

IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies" 

has been extended. 

The event hosted by THM will take place in Zoom as live presentations Sept. 29 to Oct. 1. 

Please register until Sept. 25 by use of IEEE vTools: 

https://meetings.vtools.ieee.org/m/205571
The registration is for free. 

Preliminary program: 

https://ssbmos.blogspot.com/p/programm-2020.html and 

http://www.mos-ak.org/giessen_2020

Registered attendees will receive the Zoom link for the event a few days before via email from vTools.

Important new dates: 
1st Event Announcement: Aug. 2020 
2nd Event Announcement: Sept. 2020 
Final Workshop Program: Sept. 2020
Registration deadline (extended): Sept. 25, 2020
"Spring" MOS-AK Workshop: Sept. 29/30, 2020 
IEEE MQ: Sept. 30/Oct. 1, 2020
Symposium SB-MOS devices: Oct. 1, 2020

Best regards

Alexander Kloes

_____________________________________________________________

Prof. Dr.-Ing. Alexander Kloes

 

Technische Hochschule Mittelhessen - University of Applied Sciences

Department Electrical Engineering and Information Technology

Spokesperson of Competence Center Nanotechnology and Photonics

Director of Doctoral Theses at Universitat Rovira i Virgili, Tarragona

Wiesenstrasse 14

D-35390 Giessen

Germany

E-mail: alexander.kloes@ei.thm.de

Web: go.thm.de/dmrg-en and www.thm.de

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#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi https://t.co/ieDnhSHxZh

#TSMC's development of #2nm process technology, which is already out of its pathfinding mode, is ahead of schedule, according to industry sources https://t.co/7jiFBRomRy #semi pic.twitter.com/ieDnhSHxZh

— Wladek Grabinski (@wladek60) September 22, 2020

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from Twitter https://twitter.com/wladek60

September 22, 2020 at 11:20AM
via IFTTT

[paper] 2D Charge Density Wave Phases

Machine-Intelligence-Driven High-Throughput Prediction of 2D Charge Density Wave Phases

Arnab Kabiraj and Santanu Mahapatra*

J. Phys. Chem. Lett. 2020, 11, 15, 6291–6298

Publication Date:July 22, 2020

DOI: 10.1021/acs.jpclett.0c01846

*Nano-Scale Device Research Laboratory, IISc Bangalore, India

Abstract: Charge density wave (CDW) materials are an important subclass of two-dimensional materials exhibiting significant resistivity switching with the application of external energy. However, the scarcity of such materials impedes their practical applications in nanoelectronics. Here we combine a first-principles-based structure-searching technique and unsupervised machine learning to develop a fully automated high-throughput computational framework, which identifies CDW phases from a unit cell with inherited Kohn anomaly. The proposed methodology not only rediscovers the known CDW phases but also predicts a host of easily exfoliable CDW materials (30 materials and 114 phases) along with associated electronic structures. Among many promising candidates, we pay special attention to ZrTiSe4 and conduct a comprehensive analysis to gain insight into the Fermi surface nesting, which causes significant semiconducting gap opening in its CDW phase. Our findings could provide useful guidelines for experimentalists.

Fig: Top view of TaSe₂-H 3×3_ɸ-1.