#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020 https://t.co/zD5bzZH2cN https://t.co/g7qcnAGtjM

#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020https://t.co/zD5bzZH2cN pic.twitter.com/g7qcnAGtjM

— Wladek Grabinski (@wladek60) April 20, 2020

from Twitter https://twitter.com/wladek60

April 20, 2020 at 10:49AM
via IFTTT

#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen https://t.co/QuPlCt45YH https://t.co/XsJrid4jC7

#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen https://t.co/QuPlCt45YH pic.twitter.com/XsJrid4jC7

— Wladek Grabinski (@wladek60) April 20, 2020

from Twitter https://twitter.com/wladek60

April 20, 2020 at 09:21AM
via IFTTT

#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020 https://t.co/BQAZV3tf3C https://t.co/Eqw9tGmBDI

#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020
https://t.co/BQAZV3tf3C pic.twitter.com/Eqw9tGmBDI

— Wladek Grabinski (@wladek60) April 15, 2020

from Twitter https://twitter.com/wladek60

April 15, 2020 at 05:30PM
via IFTTT

Fwd: "It is forbidden to spit on cats during plague-time"

-------- Forwarded message FYI ---------
From: John Cooley <jcooley@zeroskew.com>
Date: Wed, Apr 15, 2020 at 5:10 PM
Subject: users on Empyrean XTop ECOs, and Cadence Tempus vs. PrimeTime

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  "It is forbidden to spit on cats during plague-time."

       - Albert Camus, French philosopher (1913 - 1960)
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 Empyrean XTop fills PrimeTime ECO hole is Best of EDA 2019 #8a
            http://www.deepchip.com/items/dac19-08a.html

 Cadence Tempus fast ECOs, sign-off, and MMMC is Best of EDA #8b
            http://www.deepchip.com/items/dac19-08b.html
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 STMicroelectronics: RDC signoff on CPU subsystem & Real Intent RDC
            http://www.deepchip.com/look/see200327-02.html
Mentor whitepaper Calibre faster through DRC deck optimization
            http://www.deepchip.com/look/see190517-01.html

#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020) https://t.co/9ikrvgQq3z https://t.co/MH0mVWdyVj

#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020)https://t.co/9ikrvgQq3z pic.twitter.com/MH0mVWdyVj

— Wladek Grabinski (@wladek60) April 15, 2020

from Twitter https://twitter.com/wladek60

April 15, 2020 at 02:51PM
via IFTTT