Fastest Integrated Circuit Doubles the Previous Record, Getting Close to One Terahertz

The 670 GHz compact circuit layout (right), alongside a detail of Northrop Grumman's 30-nanometer Indium Phosphide T-gate (left). Northrop Grumman [more]

NHK Improves Resolution of Organic TFT-driven OLED Panel

NHK Science & Technology Research Laboratories (STRL) exhibited a flexible OLED panel driven by organic TFTs at OpenHouse 2010, which took place from May 27 to 30, 2010, in Tokyo [more]

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010

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C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop:  http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies

On-line abstract submission is open with the deadline on July 15, 2010.

Further details and updates: http://www.mos-ak.org/seville/

==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
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IEEE papers in May 2010

Why the Universal Mobility Is Not

Cristoloveanu, S.  Rodriguez, N.  Gamiz, F. 
Digital Object Identifier : 10.1109/TED.2010.2046109

AbstractPlus | Full Text: PDF (717KB)

Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson–Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective fie... Read More »

Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

Akturk, A.  Holloway, M.  Potbhare, S.  Gundlach, D.  Li, B.  Goldsman, N.  Peckerar, M.  Cheung, K. P. 
Digital Object Identifier : 10.1109/TED.2010.2046458

AbstractPlus | Full Text: PDF (1193KB)

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current–voltage characteristics of 0.16- and 0.18-$muhbox{m}$ bulk MOSFETs. Our measurements indicate that these MOSFETs supply approxim... Read More »

Compact Modeling of Experimental n- and p-Channel FinFETs

Song, J.  Yuan, Y.  Yu, B.  Xiong, W.  Taur, Y. 
Digital Object Identifier : 10.1109/TED.2010.2047067

AbstractPlus | Full Text: PDF (339KB)

The analytic potential model for symmetric double-gate MOSFETs is verified and calibrated with experimental n- and p-channel FinFET data over a wide range of gate lengths and bias regions. Quantum mechanical effects are incorporated in the model to reproduce the measured $C$– $V$ characteristics. The long-channel mobility consists of both a phonon scat... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part I: Dynamic Magnetization Model

Kammerer, J.-B.  Madec, M.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047070

AbstractPlus | Full Text: PDF (410KB)

The potential application range of spintronic devices is wide. However, few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: the first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part, a... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model

Madec, M.  Kammerer, J.-B.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047071

AbstractPlus | Full Text: PDF (498KB)

The potential application range of spintronic devices is wide. However, a few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: The first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part,... Read More »

Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

Kashyap, A. S.  Mantooth, H. A.  Vo, T. A.  Mojarradi, M. 
Digital Object Identifier : 10.1109/TED.2010.2046073

AbstractPlus | Full Text: PDF (1337KB)

The cryogenic characterization (93 K/$- hbox{180} ^{circ}hbox{C}$ to 300 K/27 $^{circ}hbox{C}$) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher t... Read More »

Variability Analysis of TiN Metal-Gate FinFETs

Endo, K.  O'uchi, S.  Ishikawa, Y.  Liu, Y.  Matsukawa, T.  Sakamoto, K.  Tsukada, J.  Yamauchi, H.  Masahara, M. 
Digital Object Identifier : 10.1109/LED.2010.2047091

AbstractPlus | Full Text: PDF (116KB)

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the $V_{rm th}$ in the FinFET occurs and the standard deviations of the $V_{rm th}$ of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the $V_{rm th}$ var... Read More »

Transistor mismatch in 32 nm high-k metal-gate process

 

Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors

Kimura, M. 
Digital Object Identifier : 10.1109/LED.2010.2045221

AbstractPlus | Full Text: PDF (192KB)

We have developed an extraction technique of trap densities in thin films and at insulator interfaces of thin-film transistors (TFTs). These trap densities can be extracted and separated from capacitance–voltage and current–voltage characteristics by numerically calculating $Q = CV$ , Poisson equation, carrier density equations, and Gauss' law. The outstanding advantages are intuitive understandability and a s... Read More »

Some papers (May 2010) I've found interesting...

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

5457978abstract

Bronckers, S.;   Van der Plas, G.;   Vandersteen, G.;   Rolain, Y.;  
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium 

This paper appears in: Instrumentation and Measurement, IEEE Transactions on
Issue Date: June 2010
Volume: 59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370 
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-$muhbox{m}$ triple-well common-source complementary metal–oxide–semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 $Omega$.

Thermal shot noise in top-gated single carbon nanotube field effect transistors

5464988abstract

Chaste, J.;   Pallecchi, E.;   Morfin, P.;   Feve, G.;   Kontos, T.;   Berroir, J.-M.;   Hakonen, P.;   Placais, B.;  
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889 
Date of Current Version: 13 May 2010

The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of

13 μe/

√  Hz

in the 0.2–0.8 GHz band. 

Dielectric constants of atomically thin silicon channels with double gate

Kageshima, Hiroyuki;   Fujiwara, Akira;  
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364 
Date of Current Version: 13 May 2010

Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.

 

Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques

Lehnhardt, M.;   Hamwi, S.;   Hoping, M.;   Reinker, J.;   Riedl, T.;   Kowalsky, W.;  
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416 
Date of Current Version: 13 May 2010

The charge carrier density of the p-type doped organic semiconductor 2,7-bis(9-carbazolyl)-9,9-spirobifluorene is determined for varied doping concentrations. As p-type dopant molybdenum trioxide is used. We determine the carrier density by measuring the polaron induced optical absorption and by a capacitance-voltage analysis. We show that both results are in excellent agreement. An almost linear dependence of the charge carrier density on the doping concentration is observed. Carrier densities on the order of 10¹⁸ cm^-3 at a dopant concentration of 1 mol % can be achieved. Overall, a low doping efficiency on the order of 2%–4.5% is evidenced.

The effect of traps on the performance of graphene field-effect transistors

Zhu, J.;   Jhaveri, R.;   Woo, J. C. S.;  
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785 
Date of Current Version: 13 May 2010

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.