Showing posts with label layout optimization. Show all posts
Showing posts with label layout optimization. Show all posts

Nov 19, 2021

[paper] TFT XNOR/XOR Circuit

E. Bestelink, O. de Sagazan*, I. S. Pesch and R. A. Sporea
Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors
in IEEE TED, vol. 68, no. 10, pp. 4951-4955, Oct. 2021,
DOI: 10.1109/TED.2021.3103491.
  
Advanced Technology Institute, University of Surrey (UK)
* IETR-DMM-UMR6164, University of Rennes (F)

Abstract: A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon device fabrication is complemented by physical simulations.

Fig: Micrograph of fabricated microcrystalline MMT devices and circuits. Inset: individual MMT devices with single device (MMT) and two source control gates (SUMFGMMT). Scale bars: 500μm.

Acknowledgement: Devices were fabricated on the NanoRennes platform.

CCBY - IEEE is not the copyright holder of this material.