Showing posts with label discrete device corner and statistical SPICE models. Show all posts
Showing posts with label discrete device corner and statistical SPICE models. Show all posts

Aug 26, 2020

[paper] SiC MOSFET Corner and Statistical SPICE Model Generation

SiC MOSFET Corner and Statistical SPICE Model Generation
Canzhong He, James Victory* , Yunpeng Xiao**, Herbert De Vleeschouwer+
Elvis Zheng++, ZhiPing Hu++ 
 ISPSD, September 13-18, 2020, Vienna, Austria
DOI: 10.1109/ISPSD46842.2020.9170091

   Power Design Enablement, ON Semiconductor, Mountain Top, Pennsylvania/USA
 *Power Design Enablement, ON Semiconductor, Aschheim, Germany
**Power Design Enablement, ON Semiconductor, Shanghai, China 
 +Wide Bandgap Technology Development, ON Semiconductor, Oudenaarde, Belgium 
++Product & Test Development Center, ON Semiconductor, Suzhou, China

Abstract: This paper presents a novel approach to generate corner and statistical SPICE models for SiC MOSFETs. The technique is derived from the mature IC industry standard approach known as Backward Propagation of Variance. Physically based, scalable SiC MOSFET SPICE models are required to simulate the correlations between electrical specifications and process variations. The methodologies presented are applicable to other power discrete devices such as super-junction MOSFETs, IGBTs, and GaN HEMTs.

Fig.: SiC MOSFET (a) Cross Section, (b) Subcircuit SPICE Model