[paper] Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs

Jonghwan Lee* 

Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs

Journal of the Semiconductor & Display Technology, 

Vol. 19, No. 3. September 2020

*Department of System Semiconductor Engineering, Sangmyung University

Abstract: The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantummechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.

Fig: Implementation of the gate leakage current and noise models into the BSIM model

Appendix:

Input deck to simulate MOSFET Noise

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m1 2 1 0 0 mod1 L=10u W=10u

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vgs 1 0 dc 1.4 ac 1

vds 3 0 dc 0.3

rdd 2 3 1

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.include model.TI_nmos

.op

.dc vgs 1 5 0.5

.print dc igd(vgs)

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.ac dec 10 1 100Meq

.noise v(2) vgs dec 10 1 100Meg 1

.plot noise onoisa inoise

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.end