Showing posts with label Channel surface potential. Show all posts
Showing posts with label Channel surface potential. Show all posts

Feb 9, 2025

[paper] Lambert W function for nanoscale MOSFET modeling

A. Ortiz-Conde a, V.C.P. Silva b c, P.G.D. Agopian b c, J.A. Martino b, F.J. García-Sánchez a
Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling
Solid-State Electronics (2025) 109080,
DOI:10.1016/j.sse.2025.109080

a Solid-State Electronics Lab, Universidad Simón Bolívar, Caracas 1080 (VE)
b LSI/PSI/USP, Universidade de São Paulo, São Paulo (BR)
c Department of Electronic and Telecom. Eng., Universidade Estadual Paulista, São João Da Boa Vista (BR)

Abstract: The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved, modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.

FIG: The simulated transistor structural geometry and transfer characteristics of the three TCAD simulated nanosheet devices (symbols), together with the corresponding playbacks (lines) of the traditional model and modified model.

Data availability: Data will be made available on request.