NanoTech WCM 2009: Workshop on Compact Modeling

NanoTech WCM 2009: Workshop on Compact Modeling
May 3-7, 2009
George R. Brown Convention Center
Houston, Texas, U.S.A.

Symposium Program http://www.nsti.org/Nanotech2009/WCM2009/

NB: Late News Abstracts Due: March 27th 2009 (POSTER Presentation Only)

ESSDERC'09

ESSDERC 2009 (European Solid-State Device Research Conference) will be held in Athens, Greece from 14-18 September 2009, together with ESSCIRC 2009 (European Solid-State Circuits Conference) . The venue will be the Divani Caravel Hotel, a luxury hotel situated in the centre of Athens, and very well connected to the airport by the subway. ESSDERC (European Solid-State Device Research Conference) is the top European conference in semiconductor devices.

Due to its prestige, many researchers from outside Europe use to submit contributions to ESSDERC too.The main themes for original contributions to be submitted to ESSDERC'09 are:

-Advanced CMOS devices
-Processing and Integration
-Telecommunication and Power Devices
-Modeling and Simulation
-Characterization and Reliability
-Memories
,-MEMs, Sisplays and SoC
-Emerging non-CMOS Devices and Technologies.

This year, "Compact circuit modeling for devices and interconnects" is explicitly mentioned as one of the topics in the "Modeling and Simulation" theme.

The deadline for paper submission is April 4 2009.

ESSCIRC and ESSDERC also hold a "Fringe Poster Session" event in addition to the main conference in Athens. This Fringe forum is ideally adequate for the submissions of recent scientific progress which may, in some cases, not be ready for a full paper submission. This forum provides the opportunity to network with the ESSDERC/ESSCIRC community to discuss these ideas and latest results. Reviewing will be carried out by a sub-committee under the main Technical Programme committee, and a separate proceedings will be published on CD for this event. The deadline for submissions for the Fringe Poster Session will be 12 June 2009.

Besides, several related workshops will take place on September 19 2009 at the same location. One of them will be the Autumn MOS-AK Meeting on Compact Modeling.

And no doubt mid-September is a very nice time to visit Athens. Sunny and warm, but not too hot.

CICC'09

The 2009 IEEE Custom Integrated Circuits Conference (CICC) will take place on September 13-16, 2009, at the DoubleTree Hotel in San Jose, California, in the heart of Silicon Valley.CICC is one of the top conferences on circuit design. The main topics of the conference are Analog Circuit Design, Digital and Mixed Signal SoC/ASIP/SIP/3D, Embedded Memory, ICs for MEMs, Manufacturing, Power Management, Test, Circuit Characterization, Debug, and Reliability, Wired Communications, Wireless Designs, and Simulation and Modeling, including Compact Device Modeling. The topics of compact models for extreme environment operation SOI and multiple gate device modeling are explicitly mentioned in the Call for Papers.

The paper submission deadline is April 21.

CICC 2009 will include technical paper presentations (both oral presentations and posters), panel discussions, educational sessions as well as topcial events and exhibits.

CICC is the premier conference devoted to IC development. It is the right conference to find out how to solve design problems and improve circuit design and design techniques

CICC 2009 will intend to show the latest developments in Compact Modeling, for the training of designers and to facilitate a close interaction between designers and compact model developers. It is a wonderful city with many other attractions: golf courses, wineries, and for hikers and nature lovers, the Alum Rock Park. Besides, San Jose, which is called the "Safest Big City in America", has an intense nightlife, with many dance clubs and sports bars.

TCAD Central

Juan Sanchez (see his profile in LinkedIn) has just launched TCAD Central, which he intends to be It a wiki were users can collaborate on technology Computer-Aided Design (TCAD) topics. He also says he has obtained permission to re-publish a historical place (TCAD Central from Michael Duane), which was last updated circa 1999.
You can found all these things plus others, like some nice TCAD jokes (yes, it is actually possible to do jokes about that...) in http://www.tcadcentral.com ...

Thank you very much, Juan!

Exploration of (sub-) 45nm CMOS for Analog, RF and mm-wave Applications (ST-190)

The NANO-RF project is a European funded project in the 6th Frame Program (Priority 2 : Information Society Technology), to explore the potential of (sub-)45nm CMOS for Analog, RF and mm-wave applications. Planar bulk CMOS and FinFET technologies with different gate stacks and strain engineering have been studied. The key results of this project in the field of technology optimization for analog and RF, modeling capability for FinFET transistors and varactors, ESD protection of FinFET circuits and benchmark circuit design in planar bulk and FinFET technology will be presented.

The workshop highlights :

* Fully functional complex analog building blocks in FinFET technology (10 bit 300MS/s DAC, charge pump PLL)
* 5 GHz small band LNAs and DC-5 GHz wideband LNAs in planar bulk and FinFET technology
* 24 GHz LNA, VCO and Mixer for FinFET technology
* PSP-based compact model for FinFETs
* Optimization of the 1/f noise of high-k/metal gate planar bulk and FinFET transistors
* Optimized matching performance for narrow fin FinFET transistors
* ESD protection for FinFET circuits

Read more about the workshop pogram

The NANO-RF Project contact: Stefaan.Decoutere {@} imec.be