BSIM5

I've been having a look at the Solid-State Journal, and I've found a very interesting paper from Jin He et al. They present a charge based model: BSIM5. I strongly recommend having a look at the paper, since it is from a quite good guy and the topic is, at least, important.

MOS-AK meeting

By the way, this Friday the Spring Meeting of the MOS-AK will be held in Graz, Austria, with very interesting talks, including one on Verilog-AMS and GNU software. If there is anyone going there, please send some comments....

So long....

It has been a long time since the last entry in the blog... I regret (I mean: I'm happy...) that we've had too much work. Well, here you have a very interesting link. It is not very related to Compact Modelling, but it is VERY related to scientific communication. It is an article in the Sydney Herald Tribune reporting an study about powerpoint(tm) presentations... You should read it (it quite short)...

HiSIM model included in another simlator

Magma FineSim SPICE Supports STARC HiSIM Model with Proven 20x Faster Circuit Simulation and Nearly Exact Correlation to Silicon. Or so they say in their web. See the full press release for more details. However, I love one of the sentences: "STARC's mission is to contribute to the growth of the Japanese semiconductor industry by developing leading-edge system-on-a-chip (SoC) design technologies.". Well, I would think that their primary mission is creating value for they investors, but one never knows. Now seriously, it is good to see that people is beginning to provide support (or implementations) of HiSIM. I only hope that foundries will follow the path, instead of being stuck with good (well, perhaps not so much), old (yes it is) BSIM3.1. I know this is a version of many years ago, but I can promise you that I've been playing with a 120nm technology using it.

By the way, by the moment it seems that more people is implementing HiSIM than PSP... curious, isn't it?

Call for Grant applications at SRC

SRC-GRC is calling for grant applications in Cross-disciplinary Semiconductor Research. The role of this program is to stimulate non-traditional thinking about the issues facing the semiconductor industry. It is intended to seed new research and programs for the SRC-GRC and SRC-FCRP. Consistent with the incubator role of the initiative, these will be 1 year non-overhead bearing grants at a funding level of $40K.

The scope of this solicitation is Nanoscale CMOS-Based Architectures. The challenge: Sustaining CMOS value progression through functional scaling and system design. The deadline: may, 1st. In principle, this is not for compact models, but I think that a good proposal including compact modeling could be redacted. Why? Because new devices are required to address the challenges of the next years and there is no way to do it without good compact models. So, at least a part of a sensible proposal should include some compact modeling (if nothing more, some way to go from compact device models to compact functional models... otherwise no real achivements will be obtained but only some old techniques re-edited)

By the way, IBM India is looking for Compact Model Engineers. Have a look at their web.