Agilent Announces New HVMOS Package For IC-CAP Software

I copy part of the press release (please note the language they use):

Agilent Technologies Inc. announced the availability of a new parameter extraction solution for high voltage (HV) complementary metal oxide semiconductor (CMOS) devices used in a range of automotive and consumer products, as well as LCD and display driver applications. The HVMOS extraction package, for use with Agilent's Integrated Circuit Characterization and Analysis Program (IC-CAP) software platform, enables engineers to model HV CMOS devices using Synopsys' HSPICE simulator, HVMOS Level 66 compact model.

Implemented as a compact model in HSPICE, HVMOS Level 66 compact model outperforms most other HVMOS model solutions in speed and convergence. The HVMOS model includes all relevant physical effects unique to high-voltage operation, including symmetric and asymmetric source and drain resistances, quasi-saturation, transconductance fall off at high-gate voltage, and self-heating effects. As a result, it allows HV CMOS devices to be modeled with unparalleled DC and capacitance modeling accuracy and simulation speed. HVMOS models are used by both analog and digital designers during circuit simulation.

Source: Semiconductor Online

Statistical simulation of memories

In the last issue of electronics letters (August 2 2007, vol 43, issue 16), there is an interesting paper on statistical simulation of sub-100nm memories. Here you have the link to the abstract, and try to have a look at it. I think that this (I mean: incorporating statistical techniques into the whole model) is an issue for a good compact model to be accepted by the design community.
Otherwise, if there is no way to take into account the huge variations in modern technologies, the model will be quite useless for them.

Scaling effects on short-channel organic transistors

If you are interested in organic transistors, perhaps you will appreciate having a look at the paper "Scaling effect on the operation stability of short-channel organic single-crystal transistors", appeared in the Applied Physics Letters of 6 August 2007 (link).
As they say in the abstract: "Organic single-crystal transistors allowed the authors to investigate the essential features of short-channel devices. Rubrene single-crystal transistors with channel lengths of 500 and 100 nm exhibited good field-effect characteristics under extremely low operation voltages, although space charge limited current degrades the subthreshold properties of 100 nm devices. Furthermore, bias-stress measurements revealed the remarkable stability of organic single-crystal transistors regardless of device size. The bias-stress effect was explained by the trapping of gate-induced charges into localized density of states in the single-crystal channel."

ISCAS'08

The 2008 IEEE International Symposium of Circuits and Systems (ISCAS 2008) will be held in Seattle (Washington, USA), on 18-21 May 2008.

ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited.

ISCAS 2008 will focus on the theme "Green Circuits and Systems: Engineering the Environmental Revolution".

The deadline for regular paper submission is October 5 2007. As indicated in the Call for Papers, the scope of ISCAS 2008 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.

It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format.

On the other hand, a "rich and intersting social programme is planned". It still has to be announced. Sounds promising, anyway.

New papers about compact modeling

A number of interesting papers have been published in the August issue of Transactions on Electron Devices.

In a paper entitled "Accuracy of Surface-Potential-Based Long–Wide-Channel Thick-Base MOS Transistor Models", Bin B. Jie and Chih-Tang Sah (University of Florida, Gainesville) discuss the accuracy of several surface-potential based MOSFET models. They show that the accuracy of the approximations done in these models is not so good in the accumulation and subthreshold regimes, and they propose a new analytical model showing better accuracy in those regimes.

Ananda S. Roy, Christian C. Enz and J. -M. Sallese, researchers from the EKV team at EPFL (Lausanne, Switzerland) present an analytical noise modeling paradingm for lateral nonuniform MOSFETs. They show that in these devices the bias dependence of the noise parameters cannot be predicted by conventional Klaassen-Prins (KP)-based methods.

Modeling of irradiated devices is always a hot topic. H. T. Mebrahtu et al. present SPICE models of Fluorine-Ion irradiated CMOS devices, using the EKV MOSFET model as a basis.

In this issue we also find new modeling work on Double-Gate MOSFETs. Researchers from the University of Thessaloniki (Greece) and MINATEC (Grenoble, France) have presented a paper entitled "Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs". The doping is considered in this work. The analysis is carried out in the subthershold regime, and the mobile charge is assumed to be negligible compared to the doping charge. The model shows that Ge Double-Gate MOSFETs are more prone to short-channel effects than Si Double-Gate MOSFETs.

Finally, B. Bindu, N. DasGupta and A. DasGupta (Indian Institute of Technology, Madras) present "A Unified Model for Gate Capacitance–Voltage Characteristics and Extraction of Parameters of Si/SiGe Heterostructure pMOSFETs". This analytical model is physically-based, and shows very good agreement with experimental measurements.