Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.
May 6, 2011
Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain | Blog on EDN
Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain Blog on EDN
Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.
Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.
Apr 27, 2011
[mos-ak] MOS-AK/GSA Paris Workshop Press Release
MOS-AK/GSA Modeling Working Group Holds Spring Workshop in Paris
Experts Share Insight on Compact Device Modeling with Emphasis on
Simulation-Aware Models
Experts Share Insight on Compact Device Modeling with Emphasis on
Simulation-Aware Models
Press release: http://gsaglobal.org/news/article.asp?article=2011/0426
On-line publications: http://www.mos-ak.org/paris/
The MOS-AK/GSA Modeling Working Group has several upcoming events:
* special modeling session at the MIXDES Conference in Gliwice, Poland
(https://www.mixdes.org/Special_sessions.htm);
* autumn MOS-AK/GSA workshop in Helsinki, Finland;
* winter MOS-AK/GSA meeting in Washington, D.C., USA.
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Apr 7, 2011
TSMC lays out their 20nm roadmap, no disruption from Japan.
Cited from EDN: TSMC lays out their 20nm roadmap, no disruption from Japan.:
TSMC kicked off their annual Technology Symposium series in San Jose today. Founder, Chairman and CEO Morris Chang opened the proceedings by addressing concerns for how Japan’s disaster recovery will impact the foundry’s supply chain. Dr. Chang listed a number of issues that had been of concern; metal sputtering targets, CMP (chemical-mechanical polishing) slurry, raw silicon wafers, chemicals, tools and spare parts. However, he assured the audience, TSMC has been able to solve all supply problems and “everything is under control, no supply shortages will interrupt the production lines“.
TSMC kicked off their annual Technology Symposium series in San Jose today. Founder, Chairman and CEO Morris Chang opened the proceedings by addressing concerns for how Japan’s disaster recovery will impact the foundry’s supply chain. Dr. Chang listed a number of issues that had been of concern; metal sputtering targets, CMP (chemical-mechanical polishing) slurry, raw silicon wafers, chemicals, tools and spare parts. However, he assured the audience, TSMC has been able to solve all supply problems and “everything is under control, no supply shortages will interrupt the production lines“.
TSMC does expect an impact on their customers, however, and their customer’s customers. Dr. Chang said that there will be some effect on the industry in Q2 and possibly into Q3, but the impact would be no more than two quarters. This will add to a slight softening in the world economy; including Chinese efforts to fight inflation, problems in Europe, some economic measures in U.S., with the end result being that 2011 will be less strong than TSMC had originally thought. The company is resetting their forecast from 7% growth down to 4%.
Dr. Chang then went on to describe how the semiconductor market drivers have changed; from PCs (1980-2000), to cell phones (2000 - 2010), to today’s “killer app” - mobile products, including smartphones, tablets, and any “devices you carry around“.
Moving to more technical topics, Dr. Chang predicted that the 20nm process that they have in development will provide 2X the performance over 28nm. TSMC has also begun investigation at 14nm, and “Moore’s law still has some distance to go“, according to Chang. He also noted that the company has “significant R&D” in 3D IC technology; including 2/2.5D interposers, TSV (through-silicon vias), and what the company refers to as “system-level scaling“.
Dr. Chang concluded by comparing TSMC’s capacity (2 - 12″ fabs produce up to 260,000 wafers/month), to competitors, stating that they are building capacity but they don’t have the technology, that what competitors have is not “effective capacity“. TSMC is also working on production of 450mm wafers. Pilot production is targeted for 2013-14, with an “intercept point” for production of 20nm in 2015-16.
The 20nm roadmap
Next up on the morning’s agenda was Dr. Shang-Yi Chiang, TSMC’s Sr. VP R&D, to go over TSMC’s advanced technology roadmap. Looking out to the next process node, Dr. Chiang said that the 20nm (20G) process will be available in Q3 2012. In the meantime, TSMC will offer4 versions at 28nm; LP, HPL, G, and HPM. HPM will combine high performance and low power, the sweet spot for ARM cores according to Dr. Chiang.
Dr. Chiang said that the migration to a new process node typically adds 2-3 process modules, but 5 new modules are needed for 20nm. The 20nm process node will be the last generation for planar transistors. The most expensive 20nm process module will be the change to double patterning. TSMC has developed software that will automatically apply DFM requirements to create the 2nd mask from design data.
TSMC’s 20G and 20SoC processes will offer >2X the performance and <0.75X the switching power compared to 28HP & 28HPM. A 20nm SRAM has been fabricated, but 100% yield has not been achieved yet. At 20nm, TSMC is seeing a sidewall interface effect that can dominate interconnect delays, now that line widths are approaching the mean-free path of electrons. According to Dr. Chiang, TSMC has developed a smoothing process that minimizes the effect of electrons literally bouncing off of the walls of interconnect.
TSMC says that they are innovating to extend immersion lithography to 20nm, but that NGL (next-generation lithography) will be required for nodes <20nm. Dr. Chiang said that TSMC plans to have an ASML EUV machine, the NXE-3100 at TSMC by mid-2011.
Apr 1, 2011
Nano-KISS: Advanced CMOS Devices
26-29 April 2011, Palgongsan-DAEGU, Korea
Scientific Program nano-KISS 2011
Nano-KISS is organized by Kyungpook National University (KNU) and Grenoble Insitute of Technology (NPG) via World-Class University and Brain Korea 21 projects. Pyeongsan academy, located in the famous Palgong provincial park, is a very attractive place for combining top level lectures with scientific interactions and recreational activities. The first edition in 2010 was dedicated to advanced SOI concepts and technologies. The School topics are changed every year.The program is divided in sub-topics such as to enable full-time participation or single-day participation.
Scientific Program nano-KISS 2011
Mar 22, 2011
Build accurate Spice models for low-noise, low-power precision amplifiers
Build accurate Spice models for low-noise, low-power precision amplifiers: "
Although higher-speed amplifiers have multiple poles and zeros, this model is for a single-pole, 10-MHz amplifier. It lets you simulate the amplifier’s key ac and dc parameters. The model includes ac parameters for flicker and flatband noise, slew rate, CMRR (common-mode rejection ratio), gain, and phase. The model’s dc parameters are VOS (input offset voltage), IOS (input offset current), quiescent supply current, and output-voltage swing. The model uses the 25°C typical parameters (Reference 2). The closer you model the input stage to the actual amplifier, the more accurate your results will be. You can achieve an accurate ac representation of the amplifier’s performance using a few of the process parameters of the input-stage transistors or MOSFETs. This model’s architecture lets you model amplifiers with split supplies. There is no ground reference in any of the signal-processing blocks. After the differential-to-single-ended conversion, all internally generated node voltages are referenced to the midpoint of the power supplies, much like the actual operation of an amplifier."
System engineers require accurate models for all types of ICs, and they require Spice models to run comprehensive circuit simulations. Early Spice models had few nonlinear elements, minimizing simulation time at the cost of accuracy, but new methods let you increase the number of nonlinear elements and improve accuracy. You can create a multistage model for low-noise, low-power operational amplifiers. The model employs work from Analog Devices (Reference 1) and requires several architectural changes to model a low-noise, low-power precision amplifier. The model architecture processes the input signal through eight stages. You can easily calculate the parameters for the eight stages with a handheld calculator. To understand the model creation, you must have experience using Spice.
Although higher-speed amplifiers have multiple poles and zeros, this model is for a single-pole, 10-MHz amplifier. It lets you simulate the amplifier’s key ac and dc parameters. The model includes ac parameters for flicker and flatband noise, slew rate, CMRR (common-mode rejection ratio), gain, and phase. The model’s dc parameters are VOS (input offset voltage), IOS (input offset current), quiescent supply current, and output-voltage swing. The model uses the 25°C typical parameters (Reference 2). The closer you model the input stage to the actual amplifier, the more accurate your results will be. You can achieve an accurate ac representation of the amplifier’s performance using a few of the process parameters of the input-stage transistors or MOSFETs. This model’s architecture lets you model amplifiers with split supplies. There is no ground reference in any of the signal-processing blocks. After the differential-to-single-ended conversion, all internally generated node voltages are referenced to the midpoint of the power supplies, much like the actual operation of an amplifier."
Subscribe to:
Posts (Atom)