Job offers at GLOBALFOUNDRIES Singapore

I post here a job offer I've found, because it may interest someone... 

If you wish to apply, you can go to the original website here. Good luck!!
 

 Senior Engineer

• Assist in the ESD and LU development support for various technology nodes
• The job scope will include extensive test chip design and layout, spice model development, circuit simulations, layout verification, design database preparation and documentation
• The job scope includes R&D on new and optimized ESD solutions from a foundry perspective
• In this position, the staff will be support cross functionally teams such as IO design and ESD library development
  Other responsibilities will include:
• Investigates and develops solution for highly complex circuit level ESD problems
• Learn and evolve in any other skills and tools required to achieve challenging ESD development goals including automation, and new research areas
• Publish in relevant peer reviewed journal and conferences
• Actively pursue patent development

Engineer

• The engineer will actively pursue ESD device development and assessment of ESD and LU performance of various technologies
• The responsibilities include device definition, characterization of the ESD devices using DC, pulsed and RF testers, latch up characterization, documentation and reporting, assist internal process owners for the ESD and LU rule definition
  Other responsibilities include:
• As required, explore the need to modify any given processes, procedures or methods to develop new solutions for the foundry and its customers
• Continuously research and potentially develop new test methods and charactersation approaches.
• Publish in relevant peer reviewed journal and conferences
• Actively pursue patent development

Requirements

• Phd or Masters Degree in Physics
• 2 to 5 years of relevant working experience

Senior Engineer

• Good and demonstrated knowledge in device layout, circuit design, custom layout, and IO design
• Well versed in circuit design and layout tools (such as those from cadence or Mentor)
• Analog circuit and RF design knowledge is a plus

Engineer

• Good knowledge of microelectronics and semiconductor device physics
• Demonstrated expertise and knowledge in ESD protection design and analysis using pulsed/ ESD testers, and device design
• Experience in HV device physics, compact model simulation, and product engineering is valuable
• Candidate is required to have exceptional technical skills combined with evidence of motivation to work in ESD and LU reliability area
• Open and willing to listen to internal and external customer concerns and willing to go an extra mile to help customers succeed in their efforts to achieve required ESD and LU performance targets
• Fluency in English language is a must, with good comprehension capability
• Ability to handle anyone with a pleasant attitude and willingness to share/mentor colleagues

DATE 2010 Advance Programme is Available

DATE10 Programme
Download Conference Programme (PDF - 3 MB)
Download Fringe Meetings Programme (PDF - Coming soon)

Event Overview

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Call For Papers

2010 BIPOLAR/BiCMOS CIRCUITS AND TECHNOLOGY MEETING
Austin, Texas, USA
http://www.ieee-bctm.org
Short Course: Monday October 4, 2010, Conference: Tuesday and Wednesday October 5-6, 2010
Modeling Workshop: Thursday October 7, 2010

The Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) is a forum for technical communication focused on the needs and interests of the bipolar and BiCMOS community. Papers covering the design, performance, fabrication, testing and application of bipolar and BiCMOS integrated circuits, bipolar phenomena, and discrete bipolar devices are solicited. All papers must be suitable for a twenty-minute presentation. Text and figures must not have been presented at other conferences or published in any scientific or technical publications prior
to BCTM.
Publication in the BCTM 2010 Proceedings does not preclude publication in an IEEE journal, and authors are encouraged to do so. A Special Issue of the IEEE Journal of Solid-State Circuits will include selected papers from BCTM 2010.

Papers are solicited in the following areas:
- ANALOG / DIGITAL CIRCUIT DESIGN
- RADIO FREQUENCY CIRCUIT DESIGN
- WIRELINE COMMUNICATIONS: LAN, WAN, FDDI
- DEVICE PHYSICS
- MODELING / SIMULATION- PROCESS TECHNOLOGY

STUDENT PAPERS ARE ENCOURAGED
If you know of people who may have a paper to contribute please bring this Call
for Papers to their attention.

IMPORTANT DEADLINES FOR AUTHORS
Monday, May 3, 2010 Deadline for receipt of abstract and summary
Friday, June 11, 2010 Notification of acceptance to be sent by email
Friday, July 23, 2010 Final proceedings manuscript due

SUBMISSION AND CONTACT INFORMATION
Visit the conference website: www.ieee-bctm.org, or contact:
Jan Jopke, Conference Manager, CCS Associates, 6611 Countryside Drive, Eden
Prairie, MN 55346, USA
TEL: 1-952-934-5082, FAX: 1-952-934-6741 E-mail: ccsevents@comcast.net.

A paper in the Feb. issue of IEEE TED

A Physically Based Accurate Model for Quantum Mechanical Correction to the Surface Potential of Nanoscale MOSFETs Karim, M. A.   Haque, A.   Department of Electrical and Electronic Engineering, United International University, Dhaka; This paper appears in: Electron Devices, IEEE Transactions on Publication Date: Feb. 2010 Volume: 57,  Issue: 2 On page(s): 496-502 ISSN: 0018-9383 Digital Object Identifier: 10.1109/TED.2009.2037453 First Published: 2009-12-28 Current Version Published: 2010-01-19

Abstract We present a physically based explicit analytical model for the quantum mechanical (QM) correction to the surface potential of nanoscale metal–oxide–semiconductor (MOS) devices. The effect of wave function penetration into the gate dielectric is taken into account. Instead of using the band-gap widening approach, which indirectly includes QM correction, the proposed correction term is directly added to the semiclassical surface potential. Under accumulation bias, charges in extended states and quantized states contribute to the surface potential in different ways. The proposed QM correction considers this difference in contributions. Comparison with two existing analytical QM correction models and two self-consistent QM numerical models show that the proposed correction is more accurate than the existing analytical models. The improvement achieved under the accumulation bias is particularly significant. The gate $C$– $V$ characteristics of a number of different MOS devices have been simulated using the proposed correction. Excellent agreement with published experimental data has been observed.

Analog FastSpice RF delivers noise analysis for RF circuits

By Rick Nelson, Editor-in-Chief -- EDN, 12/22/2009

Berkeley Design Automation Inc has announced AFS RF (Analog FastSpice radio frequency), which Chief Operating Officer Paul Estrada calls the industry’s first true Spice-accurate noise-analysis tool for RF circuits. AFS RF accurately analyzes nanometer-scale device noise impact for all types of prelayout and postlayout circuits, ensuring early insight into its impact on performance, power, and area.
 Before the emergence of AFS RF, designers had to use limited-spectrum RF tools that can only approximate device noise impact on RF circuits, Estrada explains. Such approximations are increasingly inaccurate with decreasing process geometries, often becoming grossly inaccurate in nanometer-scale circuits. Circuits with sharp transitions, such as switched-capacitor filters, charge pumps, and dividers; high-frequency circuits, such as RF front-end blocks; and oscillators are especially sensitive to these inaccuracies. Without accurate analysis, designers must include expensive design margin or risk missing specifications in silicon.
 Using the industry’s first full-spectrum device-noise-analysis engine, Analog FastSpice RF provides true Spice accuracy for every run. For complex circuits, it is five to 10 times faster than traditional RF tools that can only approximate device-noise effects. AFS RF features the DNA (device noise-analysis) Advisor to characterize DNA requirements, high-capacity periodic-steady-state analysis for greater than 100,000-element postlayout circuits, full-spectrum periodic-noise analysis with true Spice accuracy, full-spectrum total oscillator-device-noise analysis capability with phase and amplitude noise, and harmonic balance for fast single-tone analysis of moderately nonlinear circuits.


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