I've just seen this post at EDN. They are talking (yes, it's second-hand talk) about a list of the 10 top analog engineers. Do you think that we could make a similar list for the 10 top Compact Modelers?
Who would you put in such a list? I'd put names of people like Chenming Hu, Erik Vittoz, who are currently in active, but I'm probably too young (;-D) to put older names....
Anyway, actually, Compact Modeling is more about teamwork than about an isolated genius... so I guess that making lists maybe makes not a lot of sense... Or does it?
Dec 22, 2009
Dec 18, 2009
Compact Modeling Principles, Techniques and Applications
Gildenblat, Gennady (Ed.)
2010, Approx. 250 p., HardcoverISBN: 978-90-481-8613-6
The book includes chapters on the MOSFET noise theory, benchmarking of MOSFET compact models, modeling of the power MOSFET, and an overview of the bipolar modeling field. It concludes with two chapters describing the variability modeling including some recent developments in the field.
Table of contents
Student group works on designs for a fully integrated wireless receiver
The group, known as the Microelectronics Students’ Group, has quickly captivated new members and is now composed of more than 20 students. They are presently working towards the design of a fully integrated wireless receiver in sub-micron CMOS.
Read more...
Read more...
Dec 11, 2009
Job offer for Modelling Engineer
I copy a job offer I found:
EM Modeling Engineer
Company: Peregrine Semiconductor
Location: San Diego, CA
Please submit resumes to kfedder@psemi.com
Job Description:
Responsible for device and package modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process technology. Job functions include: Package model development, RF passive model development, parasitic analysis, test hardware/software setup, statistical modeling, model implementation on multiple EDA platforms. The candidate will work closely with senior modeling engineers to provide a comprehensive set of models to our design engineers as well as foundry customers.
Qualifications:
Education Desired and Experience
PhD in Electrical Engineering or MSEE with 5 years experience in EM modeling.
Must have knowledge base in the following areas:
Strong understanding of electromagnetic theory.
Understanding of transmission line theory.
Experience using SPICE like circuit simulators.
Experience using EM simulators (HFSS, Sonnet, IE3D).
Basic understanding of semiconductor manufacturing.
Basic understanding of semiconductor packaging.
Demonstrated ability developing automation scripts using MATLAB, Perl, MathCad, UNIX scripting, etc.
Knowledge in one or more of the following areas is highly desirable:
EM simulation on semiconductor substrates
Package model or RF model development.
Large signal device or circuit characterization and modeling
Monte Carlo/ statistical modeling
Layout optimization for RF applications
Understanding of the following tools or similar:
Cadence Design System (Virtuoso, Analog Artist, Assura, etc)
Agilent Design System (ADS, Momentum, RFDE)
MATLAB, Perl, IC-CAP
Good written and oral communication skills.
Must be able to work well in a team environment.
Location: San Diego, CA
Please submit resumes to kfedder@psemi.com
Job Description:
Responsible for device and package modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process technology. Job functions include: Package model development, RF passive model development, parasitic analysis, test hardware/software setup, statistical modeling, model implementation on multiple EDA platforms. The candidate will work closely with senior modeling engineers to provide a comprehensive set of models to our design engineers as well as foundry customers.
Qualifications:
Education Desired and Experience
PhD in Electrical Engineering or MSEE with 5 years experience in EM modeling.
Must have knowledge base in the following areas:
Strong understanding of electromagnetic theory.
Understanding of transmission line theory.
Experience using SPICE like circuit simulators.
Experience using EM simulators (HFSS, Sonnet, IE3D).
Basic understanding of semiconductor manufacturing.
Basic understanding of semiconductor packaging.
Demonstrated ability developing automation scripts using MATLAB, Perl, MathCad, UNIX scripting, etc.
Knowledge in one or more of the following areas is highly desirable:
EM simulation on semiconductor substrates
Package model or RF model development.
Large signal device or circuit characterization and modeling
Monte Carlo/ statistical modeling
Layout optimization for RF applications
Understanding of the following tools or similar:
Cadence Design System (Virtuoso, Analog Artist, Assura, etc)
Agilent Design System (ADS, Momentum, RFDE)
MATLAB, Perl, IC-CAP
Good written and oral communication skills.
Must be able to work well in a team environment.
Dec 3, 2009
Controllable Molecular Modulation of Conductivity in Silicon-Based Devices
Tao He†, David A. Corley†, Meng Lu†, Neil Halen Di Spigna‡, Jianli He†, David P. Nackashi‡, Paul D. Franzon‡ and James M. Tour†
DOI: 10.1021/ja9002537
J. Am. Chem. Soc., 2009, 131 (29), pp 10023–10030
Abstract:
Abstract:
The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal− oxide−semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-μm thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.
DOI: 10.1021/ja9002537
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