Jun 10, 2009
International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation
The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.
This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:
• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels
The deadline for Abstract Submission is July 15 2009.
Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk
If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is August 15, 2009.
This is the only workshop especifically devoted to the compact modeling of TFT!
Jun 9, 2009
Compact modeling postdoc position at Institute of Electron Technology (Warsaw, Poland)
The Division of Silicon Microsystem and Nanostructure (http://www.ite.waw.pl/en/Z02.php) at Institute of Electron Technology (http://www.ite.waw.pl/en/index.php), Warsaw, Poland is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.
Area of work
The researcher will work in the area of compact modelling of multi-gate MOSFETs. Two main topics should be covered during the researcher stay in ITE:
- development of parameter extraction methods for multi-gate MOS devices, using I-V, C-V, G-V characteristics of sets of devices, and based on combination of global optimization (constrained or unconstrained) and local fitting approaches,
- development of parameter extraction methods based on electrical characteristics of sets of multi-gate MOS devices, which account for parameters fluctuations within a wafer; (example: extraction of MOSFETs size variations DW, DL due to systematic and/or statistic photolithography and other processes fluctuations).
The work will be done in collaboration with a leading European semiconductor foundry, and leading modelling and characterization groups from European universities.
Contract details
Temporary contract, duration 20 months, full time, starting date 1 October 2009. This postdoc post is funded by the Marie-Curie European Compact Modelling network. The net monthly salary is more than 2200 Euro/month.
Application deadline: 31 August 2009.
Contact: Dr. Daniel Tomaszewski, email: dtomasz@ite.waw.pl
Requirements
Candidates should possess either
- a Ph.D. degree or
- a M.Sc. or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor microelectronics.
Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of MOS devices
- Characterization methods of MOS devices
- Numerical simulation of MOS devices
- Numerical methods
- Programming
Area of work
The researcher will work in the area of compact modelling of multi-gate MOSFETs. Two main topics should be covered during the researcher stay in ITE:
- development of parameter extraction methods for multi-gate MOS devices, using I-V, C-V, G-V characteristics of sets of devices, and based on combination of global optimization (constrained or unconstrained) and local fitting approaches,
- development of parameter extraction methods based on electrical characteristics of sets of multi-gate MOS devices, which account for parameters fluctuations within a wafer; (example: extraction of MOSFETs size variations DW, DL due to systematic and/or statistic photolithography and other processes fluctuations).
The work will be done in collaboration with a leading European semiconductor foundry, and leading modelling and characterization groups from European universities.
Contract details
Temporary contract, duration 20 months, full time, starting date 1 October 2009. This postdoc post is funded by the Marie-Curie European Compact Modelling network. The net monthly salary is more than 2200 Euro/month.
Application deadline: 31 August 2009.
Contact: Dr. Daniel Tomaszewski, email: dtomasz@ite.waw.pl
Requirements
Candidates should possess either
- a Ph.D. degree or
- a M.Sc. or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor microelectronics.
Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of MOS devices
- Characterization methods of MOS devices
- Numerical simulation of MOS devices
- Numerical methods
- Programming
Jun 8, 2009
Compact Modeling Job Vacancy at Technical University Ilmenau, Germany
The RF & Nano Device group (http://www.tu-ilmenau.de/fakei/1342+M54099f70862.0.html) at TU Ilmenau (http://www.tu-ilmenau.de/uni/index.php) is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.
The researcher will work on compact modeling of high-frequency transistors, in
particular HEMTs (High Electron Mobility Transistor). He or she will be responsible
for the development of compact models for the large-signal high-frequency behavior of
HEMTs. This will include models for the dc current-voltage characteristics and the high-frequency large-signal behavior of HEMTs with special emphasis on the modeling of nonlinearities including the extraction of model parameters from experimental results. The work will be done in close contact to a leading European semiconductor foundry.
Contract details: Temporary contract, duration 20 months, full time, starting date 1 September 2009.
Application deadline: 31 July 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should possess either
- a Ph.D. degree or
- a Master or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of semiconductor devices
- Large-signal modeling and analysis
- Nonlinear behavior of semiconductor devices and modeling of nonlinearities.
The researcher will work on compact modeling of high-frequency transistors, in
particular HEMTs (High Electron Mobility Transistor). He or she will be responsible
for the development of compact models for the large-signal high-frequency behavior of
HEMTs. This will include models for the dc current-voltage characteristics and the high-frequency large-signal behavior of HEMTs with special emphasis on the modeling of nonlinearities including the extraction of model parameters from experimental results. The work will be done in close contact to a leading European semiconductor foundry.
Contract details: Temporary contract, duration 20 months, full time, starting date 1 September 2009.
Application deadline: 31 July 2009.
Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de
Requirements: Candidates should possess either
- a Ph.D. degree or
- a Master or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is research experience in the following areas:
- Compact modeling of semiconductor devices
- Large-signal modeling and analysis
- Nonlinear behavior of semiconductor devices and modeling of nonlinearities.
Jun 4, 2009
IEEE SCV EDS Electron Device talks for June
"Negative Bias Temperature Instability in p-MOSFETs: Fundamentals, Characterization, Materials Dependence and Modeling"
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay
Date: Tuesday, June. 9, 2009
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051.
More information at the IEEE Santa Clara Valley EDS Chapter Home Page.
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay
Date: Tuesday, June. 9, 2009
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051.
More information at the IEEE Santa Clara Valley EDS Chapter Home Page.
Jun 3, 2009
Job offers
Three nice job offers:
Microwave Device Modeling Engineer, Massachusetts
Device Modeling Engineer, Cambridgeshire
Device Simulation Engineer - Solar, Surrey
Remember that we only post these offers here as an act of good will, and we're not related in any form to any of them...
Microwave Device Modeling Engineer, Massachusetts
Device Modeling Engineer, Cambridgeshire
Device Simulation Engineer - Solar, Surrey
Remember that we only post these offers here as an act of good will, and we're not related in any form to any of them...
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