MOS-AK in San Francisco (USA)

--- 1st International MOS-AK Workshop
--- Saturday, 13 December 2008; the Westin St Francis Hotel in San Francisco
--- 1st announcement

 1st International MOS-AK Workshop on compact modeling, will be organized in San Francisco (co-located with the CMC Meeting and IEDM Conference) with aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme -compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who
are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a panel session is foreseen.

The meeting program will be availabe soon at:
http://www.mos-ak.org/sanfrancisco/

Tentative list of the speakers already includes following names (in alphabetic order):
   * Henok Abebe, MOSIS;
   * Gennady Gildenblat, ASU;
   * Hans J. Mattausch, U.Hiroshima;
   * Colin Mcandrew, Freescale;
   * Marek Mierzwinski, Tiburon;
   * Paul Jespers, UC Louvain;
   * Sadayuki Yoshitomi, Toshiba;
   * Xisheng Zhang, Accelicon;

--- Important dates:--------------------
   * 2nd announcement - Nov.10
   * Final workshop program - Dec.1
   * 1st International MOS-AK Workshop - Dec.13 at the Westin St Francis Hotel in San Francisco

Further information including recommended hotels and driving directions will be posted at the web site, soon; please visit regularly: http://www.mos-ak.org

Organizing Committee:
   * Hisayo S. Momose; Toshiba; Session Chair
   * Herve Jaouen, STM; Session Chair
   * Ehrenfried Seebacher, austriamicrosystems; Panel Session Chair
   * Tim K. Smith; Accelicon; Local Arrangement Chair
   * Wladek Grabinski, GMC Suisse; Workshop Manager

Another job offer in compact modelling

Well, it seems we're in a boom... I post another one taken from LindekIn:

Requirement:
This work involves theoretical understanding of quantum effects in 22 nm scale devices; these include carrier transport, geometry and material dependent and structure calculations, role of metal and high-k material
interfaces, role of high-k on bandstructure and related phenomena to enable
development of 22 nm scale devices.

Candidates to be considered for this area are required to have a strong understanding of semiconductor physics and quantum effects in nanodevices.
The candidates are also expected to have a strong background in devices
physics, electronic structure methods, numerical programming, hands on
experience with ab-initio modeling tools, and computer programming in mixed language environment.

Should have Ph.D/MS in Physics, Electrical Engineering, Applied Physics, Computer Science, or Theoretical Materials Science.

For more details, visit the page where the offer is posted.... and polish your CV!

Job on Compact Modeling

Here you have an offer I've got from a groupmail in LinkedIn (please note that we're only posting it because it seems interesting to all those working on Compact Modeling, and looking for a change of position. We're in no way related to the people making the offer):

Looking for R&D Engineers for transistor level (MOSFET, FinFET, etc) research.(View discussion in LinkedIn.)

- PhD or MSc Microelectronics / Semiconductor Physics or equivalent
- Device Modeling/Simulation (TCAD)
- R&D experience with Universities or Fab/Foundry

Multiple vacancies in multiple Asian locations available. Email alex@maxima.com.sg for details.

[mos-ak] Edinburgh on-line publications

I post an e-mail from Wladek Grabinski (MOS-AK), in the MOS-AK googlegroups:

The MOS-AK Edinburgh Workshop's presentations are available on-line
please visit:
http://www.mos-ak.org/edinburgh/

I would like to take this opportunity and thank all speakers and presenters for their valuable contribution to the MOS-AK/ESSDERC/ESSCIRC workshop.

Let me also acknowledge the workshop sponsors (Accelicon, Tanner, X-FAB and SUSS) for their generous financial support as well as the conference organizers for their support, smooth organization and perfect logistic of our modeling event, which is an unique platform for continuous promotion of local, European compact modeling activities.

You are more than welcome to attend and contribute to coming events:

# 1st International MOS-AK Workshop in San Francisco
http://www.mos-ak.org/sanfrancisco/

# MOS-AK Spring'09 Meeting
http://www.mos-ak.org/frankfurt_o/

On the way to Plastic computation

I've found (out of sheer luck, I must say) a very nice paper in the IEEE Circuits and Systems Magazine. The topic: Plastic electronics, one of my fixations, even if I think that it will be used mainly for large-area applications. The paper I'm talking about (On the way to plastic computation) is a quite complete paper, from fabrication to circuit design using a commercial soft (Cadence).

The only point I find improvable (a lot) is that they are not doing a good job in the references, and they miss a lot of the field. However, as I've said, the paper is very interesting (not for the technical aspects, but this is a magazine...), since it's the first time I see a paper presenting the full design cycle...