IEEE TED and TNT Special Issue on Nanowire Electronics

IEEE Transactions on Electron Devices and IEEE Transactions on Nanotechnology have published a Call for Papers for a Joint Special Issue on Nanowire Electronics.

Suggested topics include Devices, Technology, Applications, Modeling and Quantum Simulations. Compact modeling for circuit design is explicitly mentioned as one of the topics.

The deadline for paper submission is April 30 2008, and the publication date will be November 2008.

New papers (APL)

Some new interesting papers on this month issue of Applied Physics Letters (APL):

Threshold voltage stability of organic field-effect transistors for various chemical species in the insulator surface
Kouji Suemori, Sei Uemura, Manabu Yoshida, Satoshi Hoshino, Noriyuki Takada, Takehito Kodzasa, and Toshihide Kamata
Appl. Phys. Lett. 91, 192112 (2007) (3 pages)
Abstract

High performance n-channel thin-film transistors with an amorphous phase C₆₀ film on plastic substrate
Jong H. Na, M. Kitamura, and Y. Arakawa
Appl. Phys. Lett. 91, 193501 (2007) (3 pages)
Abstract

The influence of visible light on transparent zinc tin oxide thin film transistors
P. Görrn, M. Lehnhardt, T. Riedl, and W. Kowalsky
Appl. Phys. Lett. 91, 193504 (2007) (3 pages)
Abstract

Flexible programmable logic gate using organic ferroelectric multilayer
Satoshi Horie, Kei Noda, Hirofumi Yamada, Kazumi Matsushige, Kenji Ishida, and Shuichiro Kuwajima
Appl. Phys. Lett. 91, 193506 (2007) (3 pages)
Abstract

Numerical modeling study of the unipolar accumulation transistor
Stephen J. Fonash, Md Mash-hud Iqbal, Florin Udrea, and Piero Migliorato
Appl. Phys. Lett. 91, 193508 (2007) (3 pages)
Abstract

Interface effects on the external quantum efficiency of organic bulk heterojunction photodetectors
Y. Kim, M. Ballarotto, D. Park, M. Du, W. Cao, C. H. Lee, W. N. Herman, and D. B. Romero
Appl. Phys. Lett. 91, 193510 (2007) (3 pages)
Abstract

New online demo and tutorial from Mentor

Two new product demos/tutorials have been added to Mentor's online event library. Both events are available on-demand and you can attend one or both at your convenience. »   Online Tutorial: Approaching Yield in the Nanometer Age The Framework for an extensible DFM Methodology. Overview: As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance. In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself. What you will learn: This tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. DFM Tools demonstrated: Calibre YieldAnalyzer Calibre YieldEnhancer Calibre YieldServer Register/Play Tutorial   »   Product Demo: Calibre LVS Integrated Design Debug Environment Overview: This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow. What you will learn: How to easily track down IC design errors using Calibre LVS How to identify the locations of these errors in your design environment How Calibre interacts with the Cadence Virtuoso design creation environment How Calibre LVS can improve your productivity by reducing your LVS debugging time Tools demonstrated: Calibre LVS to verify your IC design Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment Calibre Interactive as a launch platform to re-run your verification once the design has been fixed Register/Play Demo

Mentor Graphics Corporation Website: http://www.mentor.com/products/ic_nanometer_design Email: DSM_info@mentor.com

IWCM'08

The 5th International Workshop on Compact Modeling (IWCM 2008) will be held in the Seoul (Korea) on January 21 2008. The venue will be the Korean Convention & Exhibition Centre (COEX) in Seoul

IWCM is an interesting forum to present and discuss the recent advances in compact modeling and simulation of semiconductor devices and integrated circuits. Actually IWCM is one of the few existing Workshops devoted mostly to compact modeling, and the only one who takes place in Asia.

IWCM is collocated with the 13th Asian and South Pacific Design Automation Conference (ASP-DAC'08).

The topics of IWCM are:
- Compact modeling for all kinds of devices
- Parameter extraction methodology and strategy
- Circuit simulation techniques

Abstracts should be submitted by November 2007.

The invited speakers will be: W. Fichtner (Synopsys, USA), M. Miura-Mattausch (Hiroshima University, Japan) and Y. J. Park (Seoul National University, Korea)

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Cadence Announces Academic Network To Promote Electronic Design Competency In Europe

San Jose, CA and Feldkirchen, Germany -- Cadence Design Systems, GmbH announced the formation of an academic network in Europe to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. This initiative will establish a knowledge network among selected European universities, research institutes, industry advisors and Cadence to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic circuits. Universities were selected with particular strengths and competencies in mind-- such as analog mixed-signal, radio frequency (RF), and low power design, all of which have been identified as key challenges for the coming years by the electronics industry. Under the initiative, Cadence will provide software, training and design methodology instruction to each of the institutions. Trained on the latest techniques with leading-edge software, the universities will then share their knowledge with other academic and research institutions. Students from these universities will graduate with an in-depth knowledge of how to tackle the pressing design issues that the industry is facing, learned on the most advanced design automation products available today. So far three universities have joined the network in lead roles: The University of Heidelberg will lead high-level verification methodology; the Technical University of Ilmenau will concentrate on RF design methodology; and the Albert-Ludwigs-University of Freiburg will be the lead university for analog mixed-signal methodology. Planning to join the initiative shortly are the Polytechnic University of Bucharest, Romania, the University of Bristol, UK, and the University of Pavia in Italy. "Our high standards in teaching and research have led Cadence to select us to be the lead university for analog mixed-signal methodology," said Prof. Dr.-Ing. Yiannos Manoli, head of the Microelectronics Group at IMTEK, University of Freiburg and Director of HSG-IMIT. "The increasing demand for highly skilled graduates in microelectronic design requires a solid and broad theoretical knowledge combined with a practical skill set in state-of-the-art techniques. Being part of this network will enable us to instruct our students using leading-edge technology." Sean Redmond, vice president, EMEA for Cadence, said: "With the increase in development of complex industrial electronic systems, our customers are finding that they need engineers with broad technology competence. This network provides an exchange platform for the industry, academia and Cadence to stimulate the use of leading-edge technology at these universities. We are enthusiastic about this initiative and believe that the broad portfolio of Cadence solutions provides a perfect instrument to transfer up-to-date design methodology." SOURCE: RF Globalnet, Cadence Design Systems, Inc.

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