Showing posts with label Threshold voltage. Show all posts
Showing posts with label Threshold voltage. Show all posts
May 24, 2024

[paper] Rapid MOSFET Threshold Voltage Testing

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Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris Rapid MOSFET Threshold Voltage Testing for High Throughput Semic...
Apr 3, 2024

[paper] CMOS Technology for Analog Applications in High Energy Physics

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Gianluca Traversi, Luigi Gaioni, Lodovico Ratti, Valerio Re and Elisa Riceputi Characterization of a 28 nm CMOS Technology for Analog Applic...
Jun 13, 2023

[paper] FDSOI Threshold Voltage Model

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Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2, Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE) No...
Mar 16, 2022

[paper] Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs

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Sujit K. Singh, Sumreti Gupta, Reinaldo A. Vega* and Abhisek Dixit Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS Fin...
Jun 8, 2021

[paper] MOSFET Threshold Voltage Extraction

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Nikolaos Makris and Matthias Bucher (IEEE Member) On MOSFET Threshold Voltage Extraction  Over the Full Range of Drain Voltage Based on Gm/I...
Nov 30, 2020

[paper] The advantages of p-GaN channel/Al2O3 gate insulator

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Maria Ruzzarin,1, Carlo De Santi,1 Feng Yu,2 Muhammad Fahlesa Fatahilah,2 Klaas Strempel,2 Hutomo Suryo Wasisto,2 Andreas Waag,2 Gaudenzio M...
Nov 2, 2020

[paper] Process Induced Vt Variability

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Mandar S. Bhoir, Member, IEEE, Thomas Chiarella, Jerome Mitard, Naoto Horiguchi, Member, IEEE, and Nihar Ranjan Mohapatra, Senior Member, IE...
Jul 22, 2020

[paper] LF Noise Characterization of Ge n-Channel FinFETs

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Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, I...
Mar 30, 2020

conference paper reached 700 reads

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M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion,"  2007 IEEE Design and Diagnostics...
1 comment:
Aug 18, 2017

[paper] Improvements to a compact MOSFET model for design by hand

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Improvements to a compact MOSFET model for design by hand A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha ...
Aug 1, 2017

[paper] Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

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T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi Circuit-level simulation methodology for Random Telegraph ...